511 lines
14 KiB
C
511 lines
14 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/***************************************************************************
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* Copyright (C) 2013 Andes Technology *
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* Hsiangkai Wang <hkwang@andestech.com> *
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***************************************************************************/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include "breakpoints.h"
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#include "nds32_cmd.h"
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#include "nds32_aice.h"
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#include "nds32_v3.h"
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#include "nds32_v3_common.h"
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static int nds32_v3_activate_hardware_breakpoint(struct target *target)
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{
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struct nds32_v3_common *nds32_v3 = target_to_nds32_v3(target);
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struct aice_port_s *aice = target_to_aice(target);
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struct breakpoint *bp;
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int32_t hbr_index = nds32_v3->next_hbr_index;
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for (bp = target->breakpoints; bp; bp = bp->next) {
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if (bp->type == BKPT_SOFT) {
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/* already set at nds32_v3_add_breakpoint() */
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continue;
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} else if (bp->type == BKPT_HARD) {
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hbr_index--;
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/* set address */
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aice_write_debug_reg(aice, NDS_EDM_SR_BPA0 + hbr_index, bp->address);
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/* set mask */
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aice_write_debug_reg(aice, NDS_EDM_SR_BPAM0 + hbr_index, 0);
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/* set value */
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aice_write_debug_reg(aice, NDS_EDM_SR_BPV0 + hbr_index, 0);
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if (nds32_v3->nds32.memory.address_translation)
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/* enable breakpoint (virtual address) */
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aice_write_debug_reg(aice, NDS_EDM_SR_BPC0 + hbr_index, 0x2);
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else
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/* enable breakpoint (physical address) */
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aice_write_debug_reg(aice, NDS_EDM_SR_BPC0 + hbr_index, 0xA);
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LOG_DEBUG("Add hardware BP %" PRId32 " at %08" TARGET_PRIxADDR, hbr_index,
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bp->address);
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} else {
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return ERROR_FAIL;
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}
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}
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return ERROR_OK;
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}
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static int nds32_v3_deactivate_hardware_breakpoint(struct target *target)
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{
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struct nds32_v3_common *nds32_v3 = target_to_nds32_v3(target);
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struct aice_port_s *aice = target_to_aice(target);
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struct breakpoint *bp;
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int32_t hbr_index = nds32_v3->next_hbr_index;
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for (bp = target->breakpoints; bp; bp = bp->next) {
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if (bp->type == BKPT_SOFT) {
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continue;
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} else if (bp->type == BKPT_HARD) {
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hbr_index--;
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/* disable breakpoint */
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aice_write_debug_reg(aice, NDS_EDM_SR_BPC0 + hbr_index, 0x0);
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} else {
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return ERROR_FAIL;
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}
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LOG_DEBUG("Remove hardware BP %" PRId32 " at %08" TARGET_PRIxADDR, hbr_index,
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bp->address);
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}
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return ERROR_OK;
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}
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static int nds32_v3_activate_hardware_watchpoint(struct target *target)
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{
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struct aice_port_s *aice = target_to_aice(target);
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struct nds32_v3_common *nds32_v3 = target_to_nds32_v3(target);
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struct watchpoint *wp;
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int32_t wp_num = 0;
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uint32_t wp_config = 0;
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bool ld_stop, st_stop;
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if (nds32_v3->nds32.global_stop)
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ld_stop = st_stop = false;
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for (wp = target->watchpoints; wp; wp = wp->next) {
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if (wp_num < nds32_v3->used_n_wp) {
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wp->mask = wp->length - 1;
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if ((wp->address % wp->length) != 0)
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wp->mask = (wp->mask << 1) + 1;
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if (wp->rw == WPT_READ)
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wp_config = 0x3;
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else if (wp->rw == WPT_WRITE)
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wp_config = 0x5;
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else if (wp->rw == WPT_ACCESS)
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wp_config = 0x7;
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/* set/unset physical address bit of BPCn according to PSW.DT */
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if (nds32_v3->nds32.memory.address_translation == false)
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wp_config |= 0x8;
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/* set address */
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aice_write_debug_reg(aice, NDS_EDM_SR_BPA0 + wp_num,
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wp->address - (wp->address % wp->length));
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/* set mask */
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aice_write_debug_reg(aice, NDS_EDM_SR_BPAM0 + wp_num, wp->mask);
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/* enable watchpoint */
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aice_write_debug_reg(aice, NDS_EDM_SR_BPC0 + wp_num, wp_config);
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/* set value */
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aice_write_debug_reg(aice, NDS_EDM_SR_BPV0 + wp_num, 0);
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LOG_DEBUG("Add hardware watchpoint %" PRId32 " at %08" TARGET_PRIxADDR " mask %08" PRIx32,
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wp_num, wp->address, wp->mask);
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wp_num++;
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} else if (nds32_v3->nds32.global_stop) {
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if (wp->rw == WPT_READ)
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ld_stop = true;
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else if (wp->rw == WPT_WRITE)
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st_stop = true;
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else if (wp->rw == WPT_ACCESS)
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ld_stop = st_stop = true;
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}
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}
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if (nds32_v3->nds32.global_stop) {
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uint32_t edm_ctl;
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aice_read_debug_reg(aice, NDS_EDM_SR_EDM_CTL, &edm_ctl);
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if (ld_stop)
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edm_ctl |= 0x10;
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if (st_stop)
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edm_ctl |= 0x20;
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aice_write_debug_reg(aice, NDS_EDM_SR_EDM_CTL, edm_ctl);
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}
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return ERROR_OK;
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}
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static int nds32_v3_deactivate_hardware_watchpoint(struct target *target)
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{
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struct aice_port_s *aice = target_to_aice(target);
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struct nds32_v3_common *nds32_v3 = target_to_nds32_v3(target);
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int32_t wp_num = 0;
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struct watchpoint *wp;
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bool clean_global_stop = false;
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for (wp = target->watchpoints; wp; wp = wp->next) {
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if (wp_num < nds32_v3->used_n_wp) {
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/* disable watchpoint */
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aice_write_debug_reg(aice, NDS_EDM_SR_BPC0 + wp_num, 0x0);
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LOG_DEBUG("Remove hardware watchpoint %" PRId32 " at %08" TARGET_PRIxADDR
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" mask %08" PRIx32, wp_num,
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wp->address, wp->mask);
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wp_num++;
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} else if (nds32_v3->nds32.global_stop) {
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clean_global_stop = true;
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}
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}
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if (clean_global_stop) {
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uint32_t edm_ctl;
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aice_read_debug_reg(aice, NDS_EDM_SR_EDM_CTL, &edm_ctl);
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edm_ctl = edm_ctl & (~0x30);
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aice_write_debug_reg(aice, NDS_EDM_SR_EDM_CTL, edm_ctl);
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}
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return ERROR_OK;
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}
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static int nds32_v3_check_interrupt_stack(struct nds32 *nds32)
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{
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uint32_t val_ir0;
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uint32_t value;
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/* Save interrupt level */
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nds32_get_mapped_reg(nds32, IR0, &val_ir0);
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nds32->current_interrupt_level = (val_ir0 >> 1) & 0x3;
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if (nds32_reach_max_interrupt_level(nds32))
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LOG_ERROR("<-- TARGET ERROR! Reaching the max interrupt stack level %" PRIu32 ". -->",
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nds32->current_interrupt_level);
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/* backup $ir4 & $ir6 to avoid suppressed exception overwrite */
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nds32_get_mapped_reg(nds32, IR4, &value);
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nds32_get_mapped_reg(nds32, IR6, &value);
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return ERROR_OK;
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}
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static int nds32_v3_restore_interrupt_stack(struct nds32 *nds32)
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{
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uint32_t value;
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/* get backup value from cache */
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/* then set back to make the register dirty */
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nds32_get_mapped_reg(nds32, IR0, &value);
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nds32_set_mapped_reg(nds32, IR0, value);
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nds32_get_mapped_reg(nds32, IR4, &value);
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nds32_set_mapped_reg(nds32, IR4, value);
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nds32_get_mapped_reg(nds32, IR6, &value);
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nds32_set_mapped_reg(nds32, IR6, value);
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return ERROR_OK;
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}
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static int nds32_v3_deassert_reset(struct target *target)
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{
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int retval;
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struct aice_port_s *aice = target_to_aice(target);
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bool switch_to_v3_stack = false;
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uint32_t value_edm_ctl;
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aice_read_debug_reg(aice, NDS_EDM_SR_EDM_CTL, &value_edm_ctl);
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if (((value_edm_ctl >> 6) & 0x1) == 0) { /* reset to V2 EDM mode */
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aice_write_debug_reg(aice, NDS_EDM_SR_EDM_CTL, value_edm_ctl | (0x1 << 6));
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aice_read_debug_reg(aice, NDS_EDM_SR_EDM_CTL, &value_edm_ctl);
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if (((value_edm_ctl >> 6) & 0x1) == 1)
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switch_to_v3_stack = true;
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} else
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switch_to_v3_stack = false;
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CHECK_RETVAL(nds32_poll(target));
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if (target->state != TARGET_HALTED) {
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/* reset only */
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LOG_WARNING("%s: ran after reset and before halt ...",
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target_name(target));
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retval = target_halt(target);
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if (retval != ERROR_OK)
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return retval;
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} else {
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/* reset-halt */
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struct nds32_v3_common *nds32_v3 = target_to_nds32_v3(target);
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struct nds32 *nds32 = &(nds32_v3->nds32);
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uint32_t value;
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uint32_t interrupt_level;
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if (switch_to_v3_stack == true) {
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/* PSW.INTL-- */
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nds32_get_mapped_reg(nds32, IR0, &value);
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interrupt_level = (value >> 1) & 0x3;
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interrupt_level--;
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value &= ~(0x6);
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value |= (interrupt_level << 1);
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value |= 0x400; /* set PSW.DEX */
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nds32_set_mapped_reg(nds32, IR0, value);
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/* copy IPC to OIPC */
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if ((interrupt_level + 1) < nds32->max_interrupt_level) {
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nds32_get_mapped_reg(nds32, IR9, &value);
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nds32_set_mapped_reg(nds32, IR11, value);
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}
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}
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}
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return ERROR_OK;
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}
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static int nds32_v3_add_breakpoint(struct target *target,
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struct breakpoint *breakpoint)
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{
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struct nds32_v3_common *nds32_v3 = target_to_nds32_v3(target);
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struct nds32 *nds32 = &(nds32_v3->nds32);
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int result;
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if (breakpoint->type == BKPT_HARD) {
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/* check hardware resource */
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if (nds32_v3->n_hbr <= nds32_v3->next_hbr_index) {
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LOG_WARNING("<-- TARGET WARNING! Insert too many "
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"hardware breakpoints/watchpoints! "
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"The limit of combined hardware "
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"breakpoints/watchpoints is %" PRId32 ". -->",
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nds32_v3->n_hbr);
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LOG_WARNING("<-- TARGET STATUS: Inserted number of "
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"hardware breakpoint: %" PRId32 ", hardware "
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"watchpoints: %" PRId32 ". -->",
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nds32_v3->next_hbr_index - nds32_v3->used_n_wp,
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nds32_v3->used_n_wp);
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return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
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}
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/* update next place to put hardware breakpoint */
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nds32_v3->next_hbr_index++;
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/* hardware breakpoint insertion occurs before 'continue' actually */
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return ERROR_OK;
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} else if (breakpoint->type == BKPT_SOFT) {
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result = nds32_add_software_breakpoint(target, breakpoint);
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if (result != ERROR_OK) {
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/* auto convert to hardware breakpoint if failed */
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if (nds32->auto_convert_hw_bp) {
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/* convert to hardware breakpoint */
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breakpoint->type = BKPT_HARD;
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return nds32_v3_add_breakpoint(target, breakpoint);
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}
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}
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return result;
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} else /* unrecognized breakpoint type */
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return ERROR_FAIL;
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return ERROR_OK;
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}
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static int nds32_v3_remove_breakpoint(struct target *target,
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struct breakpoint *breakpoint)
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{
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struct nds32_v3_common *nds32_v3 = target_to_nds32_v3(target);
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if (breakpoint->type == BKPT_HARD) {
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if (nds32_v3->next_hbr_index <= 0)
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return ERROR_FAIL;
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/* update next place to put hardware breakpoint */
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nds32_v3->next_hbr_index--;
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/* hardware breakpoint removal occurs after 'halted' actually */
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return ERROR_OK;
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} else if (breakpoint->type == BKPT_SOFT) {
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return nds32_remove_software_breakpoint(target, breakpoint);
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} else /* unrecognized breakpoint type */
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return ERROR_FAIL;
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return ERROR_OK;
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}
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static int nds32_v3_add_watchpoint(struct target *target,
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struct watchpoint *watchpoint)
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{
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struct nds32_v3_common *nds32_v3 = target_to_nds32_v3(target);
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/* check hardware resource */
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if (nds32_v3->n_hbr <= nds32_v3->next_hbr_index) {
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/* No hardware resource */
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if (nds32_v3->nds32.global_stop) {
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LOG_WARNING("<-- TARGET WARNING! The number of "
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"watchpoints exceeds the hardware "
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"resources. Stop at every load/store "
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"instruction to check for watchpoint matches. -->");
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return ERROR_OK;
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}
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LOG_WARNING("<-- TARGET WARNING! Insert too many hardware "
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"breakpoints/watchpoints! The limit of combined "
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"hardware breakpoints/watchpoints is %" PRId32 ". -->",
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nds32_v3->n_hbr);
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LOG_WARNING("<-- TARGET STATUS: Inserted number of "
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"hardware breakpoint: %" PRId32 ", hardware "
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"watchpoints: %" PRId32 ". -->",
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nds32_v3->next_hbr_index - nds32_v3->used_n_wp,
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nds32_v3->used_n_wp);
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return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
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}
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/* update next place to put hardware watchpoint */
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nds32_v3->next_hbr_index++;
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nds32_v3->used_n_wp++;
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return ERROR_OK;
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}
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static int nds32_v3_remove_watchpoint(struct target *target,
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struct watchpoint *watchpoint)
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{
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struct nds32_v3_common *nds32_v3 = target_to_nds32_v3(target);
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if (nds32_v3->next_hbr_index <= 0) {
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if (nds32_v3->nds32.global_stop)
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return ERROR_OK;
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return ERROR_FAIL;
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}
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/* update next place to put hardware breakpoint */
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nds32_v3->next_hbr_index--;
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nds32_v3->used_n_wp--;
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return ERROR_OK;
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}
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static struct nds32_v3_common_callback nds32_v3_common_callback = {
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.check_interrupt_stack = nds32_v3_check_interrupt_stack,
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.restore_interrupt_stack = nds32_v3_restore_interrupt_stack,
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.activate_hardware_breakpoint = nds32_v3_activate_hardware_breakpoint,
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.activate_hardware_watchpoint = nds32_v3_activate_hardware_watchpoint,
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.deactivate_hardware_breakpoint = nds32_v3_deactivate_hardware_breakpoint,
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.deactivate_hardware_watchpoint = nds32_v3_deactivate_hardware_watchpoint,
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};
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static int nds32_v3_target_create(struct target *target, Jim_Interp *interp)
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{
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struct nds32_v3_common *nds32_v3;
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nds32_v3 = calloc(1, sizeof(*nds32_v3));
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if (!nds32_v3)
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return ERROR_FAIL;
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nds32_v3_common_register_callback(&nds32_v3_common_callback);
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nds32_v3_target_create_common(target, &(nds32_v3->nds32));
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return ERROR_OK;
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}
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/* talk to the target and set things up */
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static int nds32_v3_examine(struct target *target)
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{
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struct nds32_v3_common *nds32_v3 = target_to_nds32_v3(target);
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struct nds32 *nds32 = &(nds32_v3->nds32);
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struct aice_port_s *aice = target_to_aice(target);
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if (!target_was_examined(target)) {
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CHECK_RETVAL(nds32_edm_config(nds32));
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if (nds32->reset_halt_as_examine)
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CHECK_RETVAL(nds32_reset_halt(nds32));
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}
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uint32_t edm_cfg;
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aice_read_debug_reg(aice, NDS_EDM_SR_EDM_CFG, &edm_cfg);
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/* get the number of hardware breakpoints */
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nds32_v3->n_hbr = (edm_cfg & 0x7) + 1;
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/* low interference profiling */
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if (edm_cfg & 0x100)
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nds32_v3->low_interference_profile = true;
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else
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nds32_v3->low_interference_profile = false;
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nds32_v3->next_hbr_index = 0;
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nds32_v3->used_n_wp = 0;
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LOG_INFO("%s: total hardware breakpoint %" PRId32, target_name(target),
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nds32_v3->n_hbr);
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nds32->target->state = TARGET_RUNNING;
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nds32->target->debug_reason = DBG_REASON_NOTHALTED;
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target_set_examined(target);
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|
|
return ERROR_OK;
|
|
}
|
|
|
|
/** Holds methods for Andes1337 targets. */
|
|
struct target_type nds32_v3_target = {
|
|
.name = "nds32_v3",
|
|
|
|
.poll = nds32_poll,
|
|
.arch_state = nds32_arch_state,
|
|
|
|
.target_request_data = nds32_v3_target_request_data,
|
|
|
|
.halt = nds32_halt,
|
|
.resume = nds32_resume,
|
|
.step = nds32_step,
|
|
|
|
.assert_reset = nds32_assert_reset,
|
|
.deassert_reset = nds32_v3_deassert_reset,
|
|
|
|
/* register access */
|
|
.get_gdb_reg_list = nds32_get_gdb_reg_list,
|
|
|
|
/* memory access */
|
|
.read_buffer = nds32_v3_read_buffer,
|
|
.write_buffer = nds32_v3_write_buffer,
|
|
.read_memory = nds32_v3_read_memory,
|
|
.write_memory = nds32_v3_write_memory,
|
|
|
|
.checksum_memory = nds32_v3_checksum_memory,
|
|
|
|
/* breakpoint/watchpoint */
|
|
.add_breakpoint = nds32_v3_add_breakpoint,
|
|
.remove_breakpoint = nds32_v3_remove_breakpoint,
|
|
.add_watchpoint = nds32_v3_add_watchpoint,
|
|
.remove_watchpoint = nds32_v3_remove_watchpoint,
|
|
.hit_watchpoint = nds32_v3_hit_watchpoint,
|
|
|
|
/* MMU */
|
|
.mmu = nds32_mmu,
|
|
.virt2phys = nds32_virtual_to_physical,
|
|
.read_phys_memory = nds32_read_phys_memory,
|
|
.write_phys_memory = nds32_write_phys_memory,
|
|
|
|
.run_algorithm = nds32_v3_run_algorithm,
|
|
|
|
.commands = nds32_command_handlers,
|
|
.target_create = nds32_v3_target_create,
|
|
.init_target = nds32_v3_init_target,
|
|
.examine = nds32_v3_examine,
|
|
|
|
.get_gdb_fileio_info = nds32_get_gdb_fileio_info,
|
|
.gdb_fileio_end = nds32_gdb_fileio_end,
|
|
|
|
.profiling = nds32_profiling,
|
|
};
|