323 lines
7.7 KiB
C
323 lines
7.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright(c) 2013-2016 Intel Corporation.
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*
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* Adrian Burns (adrian.burns@intel.com)
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* Thomas Faust (thomas.faust@intel.com)
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* Ivan De Cesaris (ivan.de.cesaris@intel.com)
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* Julien Carreno (julien.carreno@intel.com)
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* Jeffrey Maxwell (jeffrey.r.maxwell@intel.com)
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*
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* Contact Information:
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* Intel Corporation
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*/
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/*
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* @file
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* This is the interface to the x86 32 bit memory and breakpoint operations.
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*/
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#ifndef OPENOCD_TARGET_X86_32_COMMON_H
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#define OPENOCD_TARGET_X86_32_COMMON_H
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#include <jtag/jtag.h>
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#include <helper/command.h>
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#include <helper/types.h>
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extern const struct command_registration x86_32_command_handlers[];
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/* for memory access */
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#define BYTE 1
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#define WORD 2
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#define DWORD 4
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#define EFLAGS_TF ((uint32_t)0x00000100) /* Trap Flag */
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#define EFLAGS_IF ((uint32_t)0x00000200) /* Interrupt Flag */
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#define EFLAGS_RF ((uint32_t)0x00010000) /* Resume Flag */
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#define EFLAGS_VM86 ((uint32_t)0x00020000) /* Virtual 8086 Mode */
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#define CSAR_DPL ((uint32_t)0x00006000)
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#define CSAR_D ((uint32_t)0x00400000)
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#define SSAR_DPL ((uint32_t)0x00006000)
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#define CR0_PE ((uint32_t)0x00000001) /* Protected Mode Enable */
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#define CR0_NW ((uint32_t)0x20000000) /* Non Write-Through */
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#define CR0_CD ((uint32_t)0x40000000) /* Cache Disable */
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#define CR0_PG ((uint32_t)0x80000000) /* Paging Enable */
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/* TODO - move back to PM specific file */
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#define PM_DR6 ((uint32_t)0xFFFF0FF0)
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#define DR6_BRKDETECT_0 ((uint32_t)0x00000001) /* B0 through B3 */
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#define DR6_BRKDETECT_1 ((uint32_t)0x00000002) /* breakpoint condition detected */
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#define DR6_BRKDETECT_2 ((uint32_t)0x00000004)
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#define DR6_BRKDETECT_3 ((uint32_t)0x00000008)
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enum {
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/* general purpose registers */
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EAX = 0,
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ECX,
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EDX,
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EBX,
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ESP,
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EBP,
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ESI,
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EDI,
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/* instruction pointer & flags */
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EIP,
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EFLAGS,
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/* segment registers */
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CS,
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SS,
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DS,
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ES,
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FS,
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GS,
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/* floating point unit registers */
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ST0,
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ST1,
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ST2,
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ST3,
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ST4,
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ST5,
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ST6,
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ST7,
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FCTRL,
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FSTAT,
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FTAG,
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FISEG,
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FIOFF,
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FOSEG,
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FOOFF,
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FOP,
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/* control registers */
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CR0,
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CR2,
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CR3,
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CR4,
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/* debug registers */
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DR0,
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DR1,
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DR2,
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DR3,
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DR6,
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DR7,
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/* descriptor tables */
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IDTB,
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IDTL,
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IDTAR,
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GDTB,
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GDTL,
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GDTAR,
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TR,
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LDTR,
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LDTB,
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LDTL,
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LDTAR,
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/* segment registers */
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CSB,
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CSL,
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CSAR,
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DSB,
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DSL,
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DSAR,
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ESB,
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ESL,
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ESAR,
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FSB,
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FSL,
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FSAR,
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GSB,
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GSL,
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GSAR,
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SSB,
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SSL,
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SSAR,
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TSSB,
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TSSL,
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TSSAR,
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/* PM control reg */
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PMCR,
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};
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#define X86_32_COMMON_MAGIC 0x86328632U
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enum {
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/* memory read/write */
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MEMRDB32 = 0,
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MEMRDB16,
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MEMRDH32,
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MEMRDH16,
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MEMRDW32,
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MEMRDW16,
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MEMWRB32,
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MEMWRB16,
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MEMWRH32,
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MEMWRH16,
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MEMWRW32,
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MEMWRW16,
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/* IO read/write */
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IORDB32,
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IORDB16,
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IORDH32,
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IORDH16,
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IORDW32,
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IORDW16,
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IOWRB32,
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IOWRB16,
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IOWRH32,
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IOWRH16,
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IOWRW32,
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IOWRW16,
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/* lakemont1 core shadow ram access opcodes */
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SRAMACCESS,
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SRAM2PDR,
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PDR2SRAM,
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WBINVD,
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};
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enum x86_core_type {
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LMT1,
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LMT3_5
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};
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struct swbp_mem_patch {
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uint8_t orig_byte;
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uint32_t swbp_unique_id;
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uint32_t physaddr;
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struct swbp_mem_patch *next;
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};
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/* TODO - probemode specific - consider removing */
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#define NUM_PM_REGS 18 /* regs used in save/restore */
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struct x86_32_common {
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unsigned int common_magic;
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void *arch_info;
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enum x86_core_type core_type;
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struct reg_cache *cache;
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struct jtag_tap *curr_tap;
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uint32_t stored_pc;
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int forced_halt_for_reset;
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int flush;
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/* pm_regs are for probemode save/restore state */
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uint32_t pm_regs[NUM_PM_REGS];
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/* working area for fastdata access */
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struct working_area *fast_data_area;
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int num_hw_bpoints;
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struct x86_32_dbg_reg *hw_break_list;
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struct swbp_mem_patch *swbbp_mem_patch_list;
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/* core probemode implementation dependent functions */
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uint8_t (*get_num_user_regs)(struct target *t);
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bool (*is_paging_enabled)(struct target *t);
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int (*disable_paging)(struct target *t);
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int (*enable_paging)(struct target *t);
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bool (*sw_bpts_supported)(struct target *t);
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int (*transaction_status)(struct target *t);
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int (*submit_instruction)(struct target *t, int num);
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int (*read_hw_reg)(struct target *t, int reg, uint32_t *regval, uint8_t cache);
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int (*write_hw_reg)(struct target *t, int reg,
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uint32_t regval, uint8_t cache);
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/* register cache to processor synchronization */
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int (*read_hw_reg_to_cache)(struct target *target, int num);
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int (*write_hw_reg_from_cache)(struct target *target, int num);
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};
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static inline struct x86_32_common *
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target_to_x86_32(struct target *target)
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{
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return target->arch_info;
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}
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bool check_not_halted(const struct target *t);
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/* breakpoint defines */
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#define MAX_DEBUG_REGS 4
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#define SW_BP_OPCODE 0xf1
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#define MAX_SW_BPTS 20
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struct x86_32_dbg_reg {
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int used;
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uint32_t bp_value;
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};
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#define DR7_G_ENABLE_SHIFT 1
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#define DR7_ENABLE_SIZE 2 /* 2 bits per debug reg */
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#define DR7_RW_SHIFT 16
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#define DR7_LENGTH_SHIFT 18
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#define DR7_RW_LEN_SIZE 4
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#define DR7_BP_EXECUTE 0 /* 00 - only on instruction execution*/
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#define DR7_BP_WRITE 1 /* 01 - only on data writes */
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/*#define DR7_RW_IORW 2 UNSUPPORTED 10 - an I/O read and I/O write */
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#define DR7_BP_READWRITE 3 /* on data read or data write */
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#define DR7_BP_LENGTH_1 0 /* 00 - 1 byte length */
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#define DR7_BP_LENGTH_2 1 /* 01 - 2 byte length */
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#define DR7_BP_LENGTH_4 3 /* 11 - 4 byte length */
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#define DR7_GLOBAL_ENABLE(val, regnum) \
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(val |= (1 << (DR7_G_ENABLE_SHIFT + (DR7_ENABLE_SIZE * (regnum)))))
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#define DR7_GLOBAL_DISABLE(val, regnum) \
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(val &= ~(3 << (DR7_ENABLE_SIZE * (regnum))))
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#define DR7_BP_FREE(val, regnum) \
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((val & (3 << (DR7_ENABLE_SIZE * (regnum)))) == 0)
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#define DR7_RESET_RWLEN_BITS(val, regnum) \
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(val &= ~(0x0f << (DR7_RW_SHIFT + DR7_RW_LEN_SIZE * (regnum))))
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#define DR7_SET_EXE(val, regnum) \
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(val &= ~(0x0f << (DR7_RW_SHIFT + DR7_RW_LEN_SIZE * (regnum))))
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#define DR7_SET_WRITE(val, regnum) \
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(val |= (DR7_BP_WRITE << (DR7_RW_SHIFT + DR7_RW_LEN_SIZE * (regnum))))
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#define DR7_SET_ACCESS(val, regnum) \
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(val |= (DR7_BP_READWRITE << (DR7_RW_SHIFT + DR7_RW_LEN_SIZE * (regnum))))
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#define DR7_SET_LENGTH(val, regnum, len) \
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(val |= (len == 1) ? (DR7_BP_LENGTH_1 << (DR7_LENGTH_SHIFT + DR7_RW_LEN_SIZE * (regnum))) : \
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(len == 2) ? (DR7_BP_LENGTH_2 << (DR7_LENGTH_SHIFT + DR7_RW_LEN_SIZE * (regnum))) : \
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(DR7_BP_LENGTH_4 << (DR7_LENGTH_SHIFT + DR7_RW_LEN_SIZE * (regnum))))
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/* public interface */
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int x86_32_get_gdb_reg_list(struct target *t,
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struct reg **reg_list[], int *reg_list_size,
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enum target_register_class reg_class);
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int x86_32_common_init_arch_info(struct target *target,
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struct x86_32_common *x86_32);
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int x86_32_common_mmu(struct target *t, int *enabled);
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int x86_32_common_virt2phys(struct target *t, target_addr_t address, target_addr_t *physical);
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int x86_32_common_read_phys_mem(struct target *t, target_addr_t phys_address,
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uint32_t size, uint32_t count, uint8_t *buffer);
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int x86_32_common_write_phys_mem(struct target *t, target_addr_t phys_address,
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uint32_t size, uint32_t count, const uint8_t *buffer);
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int x86_32_common_read_memory(struct target *t, target_addr_t addr,
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uint32_t size, uint32_t count, uint8_t *buf);
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int x86_32_common_write_memory(struct target *t, target_addr_t addr,
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uint32_t size, uint32_t count, const uint8_t *buf);
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int x86_32_common_read_io(struct target *t, uint32_t addr,
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uint32_t size, uint8_t *buf);
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int x86_32_common_write_io(struct target *t, uint32_t addr,
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uint32_t size, const uint8_t *buf);
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int x86_32_common_add_breakpoint(struct target *t, struct breakpoint *bp);
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int x86_32_common_remove_breakpoint(struct target *t, struct breakpoint *bp);
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int x86_32_common_add_watchpoint(struct target *t, struct watchpoint *wp);
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int x86_32_common_remove_watchpoint(struct target *t, struct watchpoint *wp);
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void x86_32_common_reset_breakpoints_watchpoints(struct target *t);
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#endif /* OPENOCD_TARGET_X86_32_COMMON_H */
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