178 lines
4.1 KiB
C
178 lines
4.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/***************************************************************************
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* Copyright (C) 2005 by Dominic Rath *
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* Dominic.Rath@gmx.de *
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* *
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* Copyright (C) 2007,2008 Øyvind Harboe *
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* oyvind.harboe@zylin.com *
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***************************************************************************/
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#ifndef OPENOCD_TARGET_XSCALE_H
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#define OPENOCD_TARGET_XSCALE_H
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#include "arm.h"
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#include "armv4_5_mmu.h"
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#include "trace.h"
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#define XSCALE_COMMON_MAGIC 0x58534341U
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/* These four JTAG instructions are architecturally defined.
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* Lengths are core-specific; originally 5 bits, later 7.
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*/
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#define XSCALE_DBGRX 0x02
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#define XSCALE_DBGTX 0x10
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#define XSCALE_LDIC 0x07
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#define XSCALE_SELDCSR 0x09
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/* Possible CPU types */
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#define XSCALE_IXP4XX_PXA2XX 0x0
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#define XSCALE_PXA3XX 0x4
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enum xscale_debug_reason {
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XSCALE_DBG_REASON_GENERIC,
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XSCALE_DBG_REASON_RESET,
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XSCALE_DBG_REASON_TB_FULL,
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};
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enum xscale_trace_entry_type {
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XSCALE_TRACE_MESSAGE = 0x0,
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XSCALE_TRACE_ADDRESS = 0x1,
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};
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struct xscale_trace_entry {
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uint8_t data;
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enum xscale_trace_entry_type type;
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};
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struct xscale_trace_data {
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struct xscale_trace_entry *entries;
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int depth;
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uint32_t chkpt0;
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uint32_t chkpt1;
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uint32_t last_instruction;
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unsigned int num_checkpoints;
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struct xscale_trace_data *next;
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};
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enum trace_mode {
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XSCALE_TRACE_DISABLED,
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XSCALE_TRACE_FILL,
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XSCALE_TRACE_WRAP
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};
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struct xscale_trace {
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struct image *image; /* source for target opcodes */
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struct xscale_trace_data *data; /* linked list of collected trace data */
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int buffer_fill; /* maximum number of trace runs to read */
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int fill_counter; /* running count during trace collection */
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enum trace_mode mode;
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enum arm_state core_state; /* current core state (ARM, Thumb) */
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};
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struct xscale_common {
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unsigned int common_magic;
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/* armv4/5 common stuff */
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struct arm arm;
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/* XScale registers (CP15, DBG) */
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struct reg_cache *reg_cache;
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/* current state of the debug handler */
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uint32_t handler_address;
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/* target-endian buffers with exception vectors */
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uint32_t low_vectors[8];
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uint32_t high_vectors[8];
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/* static low vectors */
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uint8_t static_low_vectors_set; /* bit field with static vectors set by the user */
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uint8_t static_high_vectors_set; /* bit field with static vectors set by the user */
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uint32_t static_low_vectors[8];
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uint32_t static_high_vectors[8];
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/* DCache cleaning */
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uint32_t cache_clean_address;
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/* whether hold_rst and ext_dbg_break should be set */
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int hold_rst;
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int external_debug_break;
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/* breakpoint / watchpoint handling */
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int dbr_available;
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int dbr0_used;
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int dbr1_used;
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int ibcr_available;
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int ibcr0_used;
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int ibcr1_used;
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uint32_t arm_bkpt;
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uint16_t thumb_bkpt;
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uint8_t vector_catch;
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struct xscale_trace trace;
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int arch_debug_reason;
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/* MMU/Caches */
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struct armv4_5_mmu_common armv4_5_mmu;
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uint32_t cp15_control_reg;
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int fast_memory_access;
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/* CPU variant */
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int xscale_variant;
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};
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static inline struct xscale_common *
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target_to_xscale(struct target *target)
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{
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return container_of(target->arch_info, struct xscale_common, arm);
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}
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struct xscale_reg {
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int dbg_handler_number;
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struct target *target;
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};
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enum {
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XSCALE_MAINID, /* 0 */
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XSCALE_CACHETYPE,
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XSCALE_CTRL,
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XSCALE_AUXCTRL,
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XSCALE_TTB,
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XSCALE_DAC,
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XSCALE_FSR,
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XSCALE_FAR,
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XSCALE_PID,
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XSCALE_CPACCESS,
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XSCALE_IBCR0, /* 10 */
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XSCALE_IBCR1,
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XSCALE_DBR0,
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XSCALE_DBR1,
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XSCALE_DBCON,
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XSCALE_TBREG,
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XSCALE_CHKPT0,
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XSCALE_CHKPT1,
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XSCALE_DCSR,
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XSCALE_TX,
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XSCALE_RX, /* 20 */
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XSCALE_TXRXCTRL,
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};
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#define ERROR_XSCALE_NO_TRACE_DATA (-700)
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/* DCSR bit and field definitions */
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#define DCSR_TR (1 << 16)
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#define DCSR_TU (1 << 17)
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#define DCSR_TS (1 << 18)
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#define DCSR_TA (1 << 19)
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#define DCSR_TD (1 << 20)
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#define DCSR_TI (1 << 22)
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#define DCSR_TF (1 << 23)
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#define DCSR_TRAP_MASK \
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(DCSR_TF | DCSR_TI | DCSR_TD | DCSR_TA | DCSR_TS | DCSR_TU | DCSR_TR)
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#endif /* OPENOCD_TARGET_XSCALE_H */
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