117 lines
2.8 KiB
INI
117 lines
2.8 KiB
INI
# SPDX-License-Identifier: GPL-2.0-or-later
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#
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# Copyright 2010 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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#
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# under GPLv2 Only
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#
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# This is for the "at91rm9200-ek" eval board.
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#
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#
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# It has atmel at91rm9200 chip.
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source [find target/at91rm9200.cfg]
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reset_config trst_and_srst
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$_TARGETNAME configure -event gdb-attach { reset init }
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$_TARGETNAME configure -event reset-init { at91rm9200_ek_init }
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## flash bank <name> <driver> <base> <size> <chip_width> <bus_width> <target>
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set _FLASHNAME $_CHIPNAME.flash
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flash bank $_FLASHNAME cfi 0x10000000 0x00800000 2 2 $_TARGETNAME
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# The chip may run @ 32khz, so set a really low JTAG speed
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adapter speed 8
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proc at91rm9200_ek_init { } {
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# Try to run at 1khz... Yea, that slow!
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# Chip is really running @ 32khz
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adapter speed 8
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mww 0xfffffc64 0xffffffff
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## disable all clocks but system clock
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mww 0xfffffc04 0xfffffffe
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## disable all clocks to pioa and piob
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mww 0xfffffc14 0xffffffc3
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## master clock = slow cpu = slow
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## (means the CPU is running at 32khz!)
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mww 0xfffffc30 0
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## main osc enable
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mww 0xfffffc20 0x0000ff01
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## MC_PUP
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mww 0xFFFFFF50 0x00000000
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## MC_PUER: Memory controller protection unit disable
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mww 0xFFFFFF54 0x00000000
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## EBI_CFGR
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mww 0xFFFFFF64 0x00000000
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## SMC2_CSR[0]: 16bit, 2 TDF, 4 WS
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mww 0xFFFFFF70 0x00003284
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## Init Clocks
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## CKGR_PLLAR
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mww 0xFFFFFC28 0x2000BF05
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## PLLAR: 179,712000 MHz for PCK
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mww 0xFFFFFC28 0x20263E04
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sleep 100
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## PMC_MCKR
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mww 0xFFFFFC30 0x00000100
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sleep 100
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## ;MCKR : PCK/3 = MCK Master Clock = 59,904000MHz from PLLA
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mww 0xFFFFFC30 0x00000202
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sleep 100
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#========================================
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# CPU now runs at 180mhz
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# SYS runs at 60mhz.
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adapter speed 40000
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#========================================
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## Init SDRAM
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## PIOC_ASR: Configure PIOC as peripheral (D16/D31)
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mww 0xFFFFF870 0xFFFF0000
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## PIOC_BSR:
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mww 0xFFFFF874 0x00000000
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## PIOC_PDR:
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mww 0xFFFFF804 0xFFFF0000
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## EBI_CSA : CS1=SDRAM
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mww 0xFFFFFF60 0x00000002
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## EBI_CFGR:
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mww 0xFFFFFF64 0x00000000
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## SDRC_CR :
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mww 0xFFFFFF98 0x2188c155
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## SDRC_MR : Precharge All
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mww 0xFFFFFF90 0x00000002
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## access SDRAM
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mww 0x20000000 0x00000000
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## SDRC_MR : Refresh
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mww 0xFFFFFF90 0x00000004
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## access SDRAM
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mww 0x20000000 0x00000000
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## access SDRAM
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mww 0x20000000 0x00000000
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## access SDRAM
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mww 0x20000000 0x00000000
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## access SDRAM
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mww 0x20000000 0x00000000
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## access SDRAM
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mww 0x20000000 0x00000000
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## access SDRAM
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mww 0x20000000 0x00000000
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## access SDRAM
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mww 0x20000000 0x00000000
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## access SDRAM
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mww 0x20000000 0x00000000
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## SDRC_MR : Load Mode Register
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mww 0xFFFFFF90 0x00000003
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## access SDRAM
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mww 0x20000080 0x00000000
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## SDRC_TR : Write refresh rate
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mww 0xFFFFFF94 0x000002E0
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## access SDRAM
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mww 0x20000000 0x00000000
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## SDRC_MR : Normal Mode
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mww 0xFFFFFF90 0x00000000
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## access SDRAM
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mww 0x20000000 0x00000000
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}
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