66 lines
2.4 KiB
INI
66 lines
2.4 KiB
INI
# SPDX-License-Identifier: GPL-2.0-or-later
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################################################################################
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# Atmel AT91SAM9261-EK eval board
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################################################################################
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source [find mem_helper.tcl]
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source [find target/at91sam9261.cfg]
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uplevel #0 [list source [find chip/atmel/at91/hardware.cfg]]
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uplevel #0 [list source [find chip/atmel/at91/at91sam9261.cfg]]
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uplevel #0 [list source [find chip/atmel/at91/at91sam9261_matrix.cfg]]
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uplevel #0 [list source [find chip/atmel/at91/at91sam9_init.cfg]]
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# By default S1 is open and this means that NTRST is not connected.
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# The reset_config in target/at91sam9261.cfg is overridden here.
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# (or S1 must be populated with a 0 Ohm resistor)
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reset_config srst_only
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scan_chain
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$_TARGETNAME configure -event gdb-attach { reset init }
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$_TARGETNAME configure -event reset-init { at91sam9261ek_reset_init }
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$_TARGETNAME configure -event reset-start { at91sam9_reset_start }
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proc at91sam9261ek_reset_init { } {
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;# for ppla at 199 Mhz
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set config(master_pll_div) 15
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set config(master_pll_mul) 162
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;# for ppla at 239 Mhz
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;# set master_pll_div 1
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;# set master_pll_mul 13
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set val $::AT91_WDT_WDV ;# Counter Value
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set val [expr {$val | $::AT91_WDT_WDDIS}] ;# Watchdog Disable
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set val [expr {$val | $::AT91_WDT_WDD}] ;# Delta Value
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set val [expr {$val | $::AT91_WDT_WDDBGHLT}] ;# Debug Halt
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set val [expr {$val | $::AT91_WDT_WDIDLEHLT}] ;# Idle Halt
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set config(wdt_mr_val) $val
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;# EBI_CSA, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash
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set config(matrix_ebicsa_addr) $::AT91_MATRIX_EBICSA
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set config(matrix_ebicsa_val) [expr {$::AT91_MATRIX_DBPUC | $::AT91_MATRIX_CS1A_SDRAMC}]
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;# SDRAMC_CR - Configuration register
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set val $::AT91_SDRAMC_NC_9
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set val [expr {$val | $::AT91_SDRAMC_NR_13}]
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set val [expr {$val | $::AT91_SDRAMC_NB_4}]
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set val [expr {$val | $::AT91_SDRAMC_CAS_3}]
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set val [expr {$val | $::AT91_SDRAMC_DBW_32}]
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set val [expr {$val | (2 << 8)}] ;# Write Recovery Delay
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set val [expr {$val | (7 << 12)}] ;# Row Cycle Delay
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set val [expr {$val | (3 << 16)}] ;# Row Precharge Delay
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set val [expr {$val | (2 << 20)}] ;# Row to Column Delay
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set val [expr {$val | (5 << 24)}] ;# Active to Precharge Delay
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set val [expr {$val | (8 << 28)}] ;# Exit Self Refresh to Active Delay
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set config(sdram_cr_val) $val
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set config(sdram_tr_val) 0x13c
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set config(sdram_base) $::AT91_CHIPSELECT_1
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at91sam9_reset_init $config
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}
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