219 lines
8.9 KiB
INI
219 lines
8.9 KiB
INI
# SPDX-License-Identifier: GPL-2.0-or-later
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#################################################################################################
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# #
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# Author: Gary Carlson (gcarlson@carlson-minot.com) #
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# Generated for Atmel AT91SAM9G20-EK evaluation board using Atmel SAM-ICE (J-Link) version 8. #
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# #
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#################################################################################################
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# FIXME use some standard target config, maybe create one from this
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#
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# source [find target/...cfg]
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source [find target/at91sam9g20.cfg]
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set _FLASHTYPE nandflash_cs3
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# Set reset type. Note that the AT91SAM9G20-EK board has the trst signal disconnected. Therefore
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# the reset needs to be configured for "srst_only". If for some reason, a zero-ohm jumper is
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# added to the board to connect the trst signal, then this parameter may need to be changed.
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reset_config srst_only
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adapter srst delay 200
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jtag_ntrst_delay 200
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# If you don't want to execute built-in boot rom code (and there are good reasons at times not to do that) in the
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# AT91SAM9 family, the microcontroller is a lump on a log without initialization. Because this family has
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# some powerful features, we want to have a special function that handles "reset init". To do this we declare
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# an event handler where these special activities can take place.
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scan_chain
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$_TARGETNAME configure -event reset-init {at91sam9g20_reset_init}
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$_TARGETNAME configure -event reset-start {at91sam9g20_reset_start}
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# NandFlash configuration and definition
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nand device nandflash_cs3 at91sam9 $_TARGETNAME 0x40000000 0xfffffe800
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at91sam9 cle 0 22
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at91sam9 ale 0 21
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at91sam9 rdy_busy 0 0xfffff800 13
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at91sam9 ce 0 0xfffff800 14
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proc read_register {register} {
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return [read_memory $register 32 1]
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}
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proc at91sam9g20_reset_start { } {
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# Make sure that the the jtag is running slow, since there are a number of different ways the board
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# can be configured coming into this state that can cause communication problems with the jtag
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# adapter. Also since this call can be made following a "reset init" where fast memory accesses
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# are enabled, need to temporarily shut this down so that the RSTC_MR register can be written at slower
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# jtag speed without causing GDB keep alive problem.
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arm7_9 fast_memory_access disable
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adapter speed 2 ;# Slow-speed oscillator enabled at reset, so run jtag speed slow.
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halt ;# Make sure processor is halted, or error will result in following steps.
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wait_halt 10000
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mww 0xfffffd08 0xa5000501 ;# RSTC_MR : enable user reset.
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}
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proc at91sam9g20_reset_init { } {
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# At reset AT91SAM9G20 chip runs on slow clock (32.768 kHz). To shift over to a normal clock requires
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# a number of steps that must be carefully performed. The process outline below follows the
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# recommended procedure outlined in the AT91SAM9G20 technical manual.
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#
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# Several key and very important things to keep in mind:
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# The SDRAM parts used currently on the Atmel evaluation board are -75 grade parts. This
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# means the master clock (MCLK) must be at or below 133 MHz or timing errors will occur. The processor
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# core can operate up to 400 MHz and therefore PCLK must be at or below this to function properly.
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mww 0xfffffd44 0x00008000 ;# WDT_MR : disable watchdog.
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# Enable the main 18.432 MHz oscillator in CKGR_MOR register.
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# Wait for MOSCS in PMC_SR to assert indicating oscillator is again stable after change to CKGR_MOR.
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mww 0xfffffc20 0x00004001
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while { [expr {[read_register 0xfffffc68] & 0x01}] != 1 } { sleep 1 }
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# Set PLLA Register for 792.576 MHz (divider: bypass, multiplier: 43).
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# Wait for LOCKA signal in PMC_SR to assert indicating PLLA is stable.
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mww 0xfffffc28 0x202a3f01
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while { [expr {[read_register 0xfffffc68] & 0x02}] != 2 } { sleep 1 }
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# Set master system clock prescaler divide by 6 and processor clock divide by 2 in PMC_MCKR.
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# Wait for MCKRDY signal from PMC_SR to assert.
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mww 0xfffffc30 0x00000101
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while { [expr {[read_register 0xfffffc68] & 0x08}] != 8 } { sleep 1 }
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# Now change PMC_MCKR register to select PLLA.
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# Wait for MCKRDY signal from PMC_SR to assert.
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mww 0xfffffc30 0x00001302
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while { [expr {[read_register 0xfffffc68] & 0x08}] != 8 } { sleep 1 }
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# Processor and master clocks are now operating and stable at maximum frequency possible:
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# -> MCLK = 132.096 MHz
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# -> PCLK = 396.288 MHz
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# Switch over to adaptive clocking.
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adapter speed 0
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# Enable faster DCC downloads and memory accesses.
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arm7_9 dcc_downloads enable
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arm7_9 fast_memory_access enable
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# To be able to use external SDRAM, several peripheral configuration registers must
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# be modified. The first change is made to PIO_ASR to select peripheral functions
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# for D15 through D31. The second change is made to the PIO_PDR register to disable
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# this for D15 through D31.
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mww 0xfffff870 0xffff0000
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mww 0xfffff804 0xffff0000
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# The EBI chip select register EBI_CS must be specifically configured to enable the internal SDRAM controller
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# using CS1. Additionally we want CS3 assigned to NandFlash. Also VDDIO is connected physically on
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# the board to the 3.3 VDC power supply so set the appropriate register bit to notify the micrcontroller.
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mww 0xffffef1c 0x000100a
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# The AT91SAM9G20-EK evaluation board has built-in NandFlash. The exact physical timing characteristics
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# for the memory type used on the current board (MT29F2G08AACWP) can be established by setting
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# a number of registers. The first step involves setting up the general I/O pins on the processor
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# to be able to interface and support the external memory.
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mww 0xfffffc10 0x00000010 ;# PMC_PCER : enable PIOC clock
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mww 0xfffff800 0x00006000 ;# PIOC_PER : enable PIO function for 13(RDY/~BSY) and 14(~CS)
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mww 0xfffff810 0x00004000 ;# PIOC_OER : enable output on 14
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mww 0xfffff814 0x00002000 ;# PIOC_ODR : disable output on 13
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mww 0xfffff830 0x00004000 ;# PIOC_SODR : set 14 to disable NAND
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# The exact physical timing characteristics for the memory type used on the current board
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# (MT29F2G08AACWP) can be established by setting four registers in order: SMC_SETUP3,
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# SMC_PULSE3, SMC_CYCLE3, and SMC_MODE3. Computing the exact values of these registers
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# is a little tedious to do here. If you have questions about how to do this, Atmel has
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# a decent application note #6255B that covers this process.
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mww 0xffffec30 0x00020002 ;# SMC_SETUP3 : 2 clock cycle setup for NRD and NWE
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mww 0xffffec34 0x04040404 ;# SMC_PULSE3 : 4 clock cycle pulse for all signals
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mww 0xffffec38 0x00070006 ;# SMC_CYCLE3 : 7 clock cycle NRD and 6 NWE cycle
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mww 0xffffec3C 0x00020003 ;# SMC_MODE3 : NRD and NWE control, no NWAIT, 8-bit DBW,
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mww 0xffffe800 0x00000001 ;# ECC_CR : reset the ECC parity registers
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mww 0xffffe804 0x00000002 ;# ECC_MR : page size is 2112 words (word is 8 bits)
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# Identify NandFlash bank 0.
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nand probe nandflash_cs3
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# The AT91SAM9G20-EK evaluation board has built-in serial data flash also.
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# Now setup SDRAM. This is tricky and configuration is very important for reliability! The current calculations
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# are based on 2 x Micron MT48LC16M16A2-75 memory (4 M x 16 bit x 4 banks). If you use this file as a reference
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# for a new board that uses different SDRAM devices or clock rates, you need to recalculate the value inserted
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# into the SDRAM_CR register. Using the memory datasheet for the -75 grade part and assuming a master clock
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# of 132.096 MHz then the SDCLK period is equal to 7.6 ns. This means the device requires:
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#
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# CAS latency = 3 cycles
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# TXSR = 10 cycles
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# TRAS = 6 cycles
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# TRCD = 3 cycles
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# TRP = 3 cycles
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# TRC = 9 cycles
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# TWR = 2 cycles
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# 9 column, 13 row, 4 banks
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# refresh equal to or less then 7.8 us for commercial/industrial rated devices
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#
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# Thus SDRAM_CR = 0xa6339279
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mww 0xffffea08 0xa6339279
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# Next issue a 'NOP' command through the SDRAMC_MR register followed by writing a zero value into
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# the starting memory location for the SDRAM.
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mww 0xffffea00 0x00000001
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mww 0x20000000 0
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# Issue an 'All Banks Precharge' command through the SDRAMC_MR register followed by writing a zero
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# value into the starting memory location for the SDRAM.
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mww 0xffffea00 0x00000002
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mww 0x20000000 0
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# Now issue an 'Auto-Refresh' command through the SDRAMC_MR register. Follow this operation by writing
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# zero values eight times into the starting memory location for the SDRAM.
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mww 0xffffea00 0x4
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mww 0x20000000 0
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mww 0x20000000 0
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mww 0x20000000 0
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mww 0x20000000 0
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mww 0x20000000 0
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mww 0x20000000 0
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mww 0x20000000 0
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mww 0x20000000 0
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# Almost done, so next issue a 'Load Mode Register' command followed by a zero value write to the
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# the starting memory location for the SDRAM.
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mww 0xffffea00 0x3
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mww 0x20000000 0
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# Signal normal mode using the SDRAMC_MR register and follow with a zero value write the the starting
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# memory location for the SDRAM.
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mww 0xffffea00 0x0
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mww 0x20000000 0
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# Finally set the refresh rate to about every 7 us (7.5 ns x 924 cycles).
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mww 0xffffea04 0x0000039c
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}
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