204 lines
5.2 KiB
INI
204 lines
5.2 KiB
INI
# SPDX-License-Identifier: GPL-2.0-or-later
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# DM355 EVM board
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# http://focus.ti.com/docs/toolsw/folders/print/tmdsevm355.html
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# http://c6000.spectrumdigital.com/evmdm355/
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source [find target/ti_dm355.cfg]
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reset_config trst_and_srst separate
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# NOTE: disable or replace this call to dm355evm_init if you're
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# debugging new UBL code from SRAM.
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$_TARGETNAME configure -event reset-init { dm355evm_init }
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#
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# This post-reset init is called when the MMU isn't active, all IRQs
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# are disabled, etc. It should do most of what a UBL does, except for
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# loading code (like U-Boot) into DRAM and running it.
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#
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proc dm355evm_init {} {
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global dm355
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echo "Initialize DM355 EVM board"
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# CLKIN = 24 MHz ... can't talk quickly to ARM yet
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jtag_rclk 1500
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########################
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# PLL1 = 432 MHz (/8, x144)
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# ...SYSCLK1 = 216 MHz (/2) ... ARM, MJCP
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# ...SYSCLK2 = 108 MHz (/4) ... Peripherals
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# ...SYSCLK3 = 27 MHz (/16) ... VPBE, DAC
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# ...SYSCLK4 = 108 MHz (/4) ... VPSS
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# pll1.{prediv,div1,div2} are fixed
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# pll1.postdiv set in MISC (for *this* speed grade)
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set addr [dict get $dm355 pllc1]
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set pll_divs [dict create]
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dict set pll_divs div3 16
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dict set pll_divs div4 4
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pll_v02_setup $addr 144 $pll_divs
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# ARM is now running at 216 MHz, so JTAG can go faster
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jtag_rclk 20000
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########################
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# PLL2 = 342 MHz (/8, x114)
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# ....SYSCLK1 = 342 MHz (/1) ... DDR PHY at 171 MHz, 2x clock
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# pll2.{postdiv,div1} are fixed
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set addr [dict get $dm355 pllc2]
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set pll_divs [dict create]
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dict set pll_divs div1 1
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dict set pll_divs prediv 8
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pll_v02_setup $addr 114 $pll_divs
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########################
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# PINMUX
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# All Video Inputs
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davinci_pinmux $dm355 0 0x00007f55
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# All Video Outputs
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davinci_pinmux $dm355 1 0x00145555
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# EMIFA (NOTE: more could be set up for use as GPIOs)
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davinci_pinmux $dm355 2 0x00000c08
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# SPI0, SPI1, UART1, I2C, SD0, SD1, McBSP0, CLKOUTs
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davinci_pinmux $dm355 3 0x1bff55ff
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# MMC/SD0 instead of MS; SPI0
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davinci_pinmux $dm355 4 0x00000000
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########################
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# PSC setup (minimal)
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# DDR EMIF/13, AEMIF/14, UART0/19
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psc_enable 13
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psc_enable 14
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psc_enable 19
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psc_go
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########################
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# DDR2 EMIF
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# VTPIOCR impedance calibration
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set addr [dict get $dm355 sysbase]
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set addr [expr {$addr + 0x70}]
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# clear CLR, LOCK, PWRDN; wait a clock; set CLR
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mmw $addr 0 0x20c0
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mmw $addr 0x2000 0
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# wait for READY
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while { [expr {[mrw $addr] & 0x8000}] == 0 } { sleep 1 }
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# set IO_READY; then LOCK and PWRSAVE; then PWRDN
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mmw $addr 0x4000 0
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mmw $addr 0x0180 0
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mmw $addr 0x0040 0
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# NOTE: this DDR2 initialization sequence borrows from
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# both UBL 1.50 and the SPRUEH7D DDR2 EMIF spec.
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# reset (then re-enable) DDR controller
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psc_reset 13
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psc_go
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psc_enable 13
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psc_go
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# now set it up for Micron MT47H64M16HR-37E @ 171 MHz
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set addr [dict get $dm355 ddr_emif]
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# DDRPHYCR1
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mww [expr {$addr + 0xe4}] 0x50006404
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# PBBPR -- burst priority
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mww [expr {$addr + 0x20}] 0xfe
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# SDCR -- unlock boot config; init for DDR2, relock, unlock SDTIM*
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mmw [expr {$addr + 0x08}] 0x00800000 0
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mmw [expr {$addr + 0x08}] 0x0013c632 0x03870fff
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# SDTIMR0, SDTIMR1
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mww [expr {$addr + 0x10}] 0x2a923249
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mww [expr {$addr + 0x14}] 0x4c17c763
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# SDCR -- relock SDTIM*
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mmw [expr {$addr + 0x08}] 0 0x00008000
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# SDRCR -- refresh rate (171 MHz * 7.8usec)
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mww [expr {$addr + 0x0c}] 1336
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########################
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# ASYNC EMIF
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set addr [dict get $dm355 a_emif]
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# slow/pessimistic timings
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set nand_timings 0x40400204
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# fast (25% faster page reads)
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#set nand_timings 0x0400008c
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# AWCCR
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mww [expr {$addr + 0x04}] 0xff
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# CS0 == socketed NAND (default MT29F16G08FAA, 2GByte)
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mww [expr {$addr + 0x10}] $nand_timings
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# CS1 == dm9000 Ethernet
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mww [expr {$addr + 0x14}] 0x00a00505
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# NANDFCR -- only CS0 has NAND
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mww [expr {$addr + 0x60}] 0x01
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# default: both chipselects to the NAND socket are used
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nand probe 0
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nand probe 1
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########################
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# UART0
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set addr [dict get $dm355 uart0]
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# PWREMU_MGNT -- rx + tx in reset
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mww [expr {$addr + 0x30}] 0
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# DLL, DLH -- 115200 baud
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mwb [expr {$addr + 0x20}] 0x0d
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mwb [expr {$addr + 0x24}] 0x00
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# FCR - clear and disable FIFOs
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mwb [expr {$addr + 0x08}] 0x07
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mwb [expr {$addr + 0x08}] 0x00
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# IER - disable IRQs
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mwb [expr {$addr + 0x04}] 0x00
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# LCR - 8-N-1
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mwb [expr {$addr + 0x0c}] 0x03
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# MCR - no flow control or loopback
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mwb [expr {$addr + 0x10}] 0x00
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# PWREMU_MGNT -- rx + tx normal, free running during JTAG halt
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mww [expr {$addr + 0x30}] 0xe001
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########################
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# turn on icache - set I bit in cp15 register c1
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arm mcr 15 0 0 1 0 0x00051078
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}
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# NAND -- socket has two chipselects, MT29F16G08FAA puts 1GByte on each one.
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#
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# NOTE: "hwecc4" here presumes that if you're using the standard 2GB NAND
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# you either (a) have 'new' DM355 chips, with boot ROMs that don't need to
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# use "hwecc4_infix" for the UBL; or else (b) aren't updating anything that
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# needs infix layout ... like an old UBL, old U-Boot, old MVL kernel, etc.
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set _FLASHNAME $_CHIPNAME.boot
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nand device $_FLASHNAME davinci $_TARGETNAME 0x02000000 hwecc4 0x01e10000
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set _FLASHNAME $_CHIPNAME.flash
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nand device $_FLASHNAME davinci $_TARGETNAME 0x02004000 hwecc4 0x01e10000
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# FIXME
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# - support writing UBL with its header (new layout only with new ROMs)
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# - support writing ABL/U-Boot with its header (new layout)
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