321 lines
8.8 KiB
Tcl
321 lines
8.8 KiB
Tcl
# SPDX-License-Identifier: GPL-2.0-or-later
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#######################################
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# DENX M53EVK #
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# http://www.denx-cs.de/?q=M53EVK #
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# Author: Marek Vasut <marex@denx.de> #
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# Based on imx53loco.cfg #
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#######################################
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# The DENX M53EVK has on-board JTAG adapter
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source [find interface/ftdi/m53evk.cfg]
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# The DENX M53EVK board has a single i.MX53 chip
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source [find target/imx53.cfg]
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# Helper for common memory read/modify/write procedures
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source [find mem_helper.tcl]
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echo "iMX53 M53EVK board lodaded."
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# Set reset type
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reset_config trst_and_srst separate trst_open_drain srst_open_drain
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# Run at 6 MHz
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adapter speed 6000
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$_TARGETNAME configure -event "reset-assert" {
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echo "Resetting ...."
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#cortex_a dbginit
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}
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$_TARGETNAME configure -event reset-init { m53evk_init }
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global AIPS1_BASE_ADDR
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set AIPS1_BASE_ADDR 0x53F00000
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global AIPS2_BASE_ADDR
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set AIPS2_BASE_ADDR 0x63F00000
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proc m53evk_init { } {
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echo "Reset-init..."
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; # halt the CPU
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halt
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echo "HW version [format %x [mrw 0x48]]"
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dap apsel 1
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DCD
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; # ARM errata ID #468414
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set tR [arm mrc 15 0 1 0 1]
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arm mcr 15 0 1 0 1 [expr {$tR | (1<<5)}] ; # enable L1NEON bit
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init_l2cc
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init_aips
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init_clock
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dap apsel 0
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; # Force ARM state
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; #reg cpsr 0x000001D3
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arm core_state arm
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}
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# L2CC Cache setup/invalidation/disable
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proc init_l2cc { } {
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; #/* explicitly disable L2 cache */
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; #mrc 15, 0, r0, c1, c0, 1
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set tR [arm mrc 15 0 1 0 1]
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; #bic r0, r0, #0x2
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; #mcr 15, 0, r0, c1, c0, 1
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arm mcr 15 0 1 0 1 [expr {$tR & ~(1 << 2)}]
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; #/* reconfigure L2 cache aux control reg */
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; #mov r0, #0xC0 /* tag RAM */
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; #add r0, r0, #0x4 /* data RAM */
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; #orr r0, r0, #(1 << 24) /* disable write allocate delay */
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; #orr r0, r0, #(1 << 23) /* disable write allocate combine */
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; #orr r0, r0, #(1 << 22) /* disable write allocate */
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; #mcr 15, 1, r0, c9, c0, 2
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arm mcr 15 1 9 0 2 [expr {0xC4 | (1<<24) | (1<<23) | (1<<22)}]
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}
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# AIPS setup - Only setup MPROTx registers.
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# The PACR default values are good.
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proc init_aips { } {
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; # Set all MPROTx to be non-bufferable, trusted for R/W,
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; # not forced to user-mode.
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global AIPS1_BASE_ADDR
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global AIPS2_BASE_ADDR
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set VAL 0x77777777
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# dap apsel 1
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mww [expr {$AIPS1_BASE_ADDR + 0x0}] $VAL
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mww [expr {$AIPS1_BASE_ADDR + 0x4}] $VAL
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mww [expr {$AIPS2_BASE_ADDR + 0x0}] $VAL
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mww [expr {$AIPS2_BASE_ADDR + 0x4}] $VAL
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# dap apsel 0
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}
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proc init_clock { } {
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global AIPS1_BASE_ADDR
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global AIPS2_BASE_ADDR
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set CCM_BASE_ADDR [expr {$AIPS1_BASE_ADDR + 0x000D4000}]
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set CLKCTL_CCSR 0x0C
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set CLKCTL_CBCDR 0x14
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set CLKCTL_CBCMR 0x18
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set PLL1_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x00080000}]
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set PLL2_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x00084000}]
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set PLL3_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x00088000}]
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set PLL4_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x0008C000}]
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set CLKCTL_CSCMR1 0x1C
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set CLKCTL_CDHIPR 0x48
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set PLATFORM_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x000A0000}]
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set CLKCTL_CSCDR1 0x24
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set CLKCTL_CCDR 0x04
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; # Switch ARM to step clock
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mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCSR}] 0x4
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return
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echo "not returned"
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setup_pll $PLL1_BASE_ADDR 800
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setup_pll $PLL3_BASE_ADDR 400
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; # Switch peripheral to PLL3
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mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCMR}] 0x00015154
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mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCDR}] [expr {0x02888945 | (1<<16)}]
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while {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CDHIPR}]] != 0} { sleep 1 }
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setup_pll $PLL2_BASE_ADDR 400
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; # Switch peripheral to PLL2
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mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCDR}] [expr {0x00808145 | (2<<10) | (9<<16) | (1<<19)}]
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mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCMR}] 0x00016154
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; # change uart clk parent to pll2
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mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}] [expr {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}]] & 0xfcffffff | 0x01000000}]
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; # make sure change is effective
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while {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CDHIPR}]] != 0} { sleep 1 }
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setup_pll $PLL3_BASE_ADDR 216
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setup_pll $PLL4_BASE_ADDR 455
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; # Set the platform clock dividers
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mww [expr {$PLATFORM_BASE_ADDR + 0x14}] 0x00000124
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mww [expr {$CCM_BASE_ADDR + 0x10}] 0
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; # Switch ARM back to PLL 1.
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mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCSR}] 0x0
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; # make uart div=6
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mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}] [expr {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}]] & 0xffffffc0 | 0x0a}]
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; # Restore the default values in the Gate registers
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mww [expr {$CCM_BASE_ADDR + 0x68}] 0xFFFFFFFF
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mww [expr {$CCM_BASE_ADDR + 0x6C}] 0xFFFFFFFF
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mww [expr {$CCM_BASE_ADDR + 0x70}] 0xFFFFFFFF
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mww [expr {$CCM_BASE_ADDR + 0x74}] 0xFFFFFFFF
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mww [expr {$CCM_BASE_ADDR + 0x78}] 0xFFFFFFFF
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mww [expr {$CCM_BASE_ADDR + 0x7C}] 0xFFFFFFFF
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mww [expr {$CCM_BASE_ADDR + 0x80}] 0xFFFFFFFF
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mww [expr {$CCM_BASE_ADDR + 0x84}] 0xFFFFFFFF
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mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCDR}] 0x00000
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; # for cko - for ARM div by 8
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mww [expr {$CCM_BASE_ADDR + 0x60}] [expr {0x000A0000 & 0x00000F0}]
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}
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proc setup_pll { PLL_ADDR CLK } {
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set PLL_DP_CTL 0x00
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set PLL_DP_CONFIG 0x04
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set PLL_DP_OP 0x08
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set PLL_DP_HFS_OP 0x1C
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set PLL_DP_MFD 0x0C
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set PLL_DP_HFS_MFD 0x20
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set PLL_DP_MFN 0x10
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set PLL_DP_HFS_MFN 0x24
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if {$CLK == 1000} {
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set DP_OP [expr {(10 << 4) + ((1 - 1) << 0)}]
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set DP_MFD [expr {12 - 1}]
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set DP_MFN 5
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} elseif {$CLK == 850} {
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set DP_OP [expr {(8 << 4) + ((1 - 1) << 0)}]
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set DP_MFD [expr {48 - 1}]
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set DP_MFN 41
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} elseif {$CLK == 800} {
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set DP_OP [expr {(8 << 4) + ((1 - 1) << 0)}]
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set DP_MFD [expr {3 - 1}]
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set DP_MFN 1
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} elseif {$CLK == 700} {
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set DP_OP [expr {(7 << 4) + ((1 - 1) << 0)}]
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set DP_MFD [expr {24 - 1}]
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set DP_MFN 7
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} elseif {$CLK == 600} {
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set DP_OP [expr {(6 << 4) + ((1 - 1) << 0)}]
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set DP_MFD [expr {4 - 1}]
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set DP_MFN 1
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} elseif {$CLK == 665} {
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set DP_OP [expr {(6 << 4) + ((1 - 1) << 0)}]
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set DP_MFD [expr {96 - 1}]
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set DP_MFN 89
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} elseif {$CLK == 532} {
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set DP_OP [expr {(5 << 4) + ((1 - 1) << 0)}]
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set DP_MFD [expr {24 - 1}]
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set DP_MFN 13
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} elseif {$CLK == 455} {
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set DP_OP [expr {(8 << 4) + ((2 - 1) << 0)}]
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set DP_MFD [expr {48 - 1}]
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set DP_MFN 71
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} elseif {$CLK == 400} {
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set DP_OP [expr {(8 << 4) + ((2 - 1) << 0)}]
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set DP_MFD [expr {3 - 1}]
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set DP_MFN 1
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} elseif {$CLK == 216} {
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set DP_OP [expr {(6 << 4) + ((3 - 1) << 0)}]
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set DP_MFD [expr {4 - 1}]
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set DP_MFN 3
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} else {
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error "Error (setup_dll): clock not found!"
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}
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mww [expr {$PLL_ADDR + $PLL_DP_CTL}] 0x00001232
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mww [expr {$PLL_ADDR + $PLL_DP_CONFIG}] 0x2
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mww [expr {$PLL_ADDR + $PLL_DP_OP}] $DP_OP
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mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFD}] $DP_OP
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mww [expr {$PLL_ADDR + $PLL_DP_MFD}] $DP_MFD
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mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFD}] $DP_MFD
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mww [expr {$PLL_ADDR + $PLL_DP_MFN}] $DP_MFN
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mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFN}] $DP_MFN
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mww [expr {$PLL_ADDR + $PLL_DP_CTL}] 0x00001232
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while {[expr {[mrw [expr {$PLL_ADDR + $PLL_DP_CTL}]] & 0x1}] == 0} { sleep 1 }
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}
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proc CPU_2_BE_32 { L } {
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return [expr {(($L & 0x000000FF) << 24) | (($L & 0x0000FF00) << 8) | (($L & 0x00FF0000) >> 8) | (($L & 0xFF000000) >> 24)}]
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}
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# Device Configuration Data
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proc DCD { } {
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# dap apsel 1
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mww 0x53fa86f4 0x00000000 ;# GRP_DDRMODE_CTL
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mww 0x53fa8714 0x00000000 ;# GRP_DDRMODE
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mww 0x53fa86fc 0x00000000 ;# GRP_DDRPKE
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mww 0x53fa8724 0x04000000 ;# GRP_DDR_TYPE
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mww 0x53fa872c 0x00300000 ;# GRP_B3DS
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mww 0x53fa8554 0x00300000 ;# DRAM_DQM3
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mww 0x53fa8558 0x00300040 ;# DRAM_SDQS3
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mww 0x53fa8728 0x00300000 ;# GRP_B2DS
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mww 0x53fa8560 0x00300000 ;# DRAM_DQM2
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mww 0x53fa8568 0x00300040 ;# DRAM_SDQS2
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mww 0x53fa871c 0x00300000 ;# GRP_B1DS
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mww 0x53fa8594 0x00300000 ;# DRAM_DQM1
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mww 0x53fa8590 0x00300040 ;# DRAM_SDQS1
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mww 0x53fa8718 0x00300000 ;# GRP_B0DS
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mww 0x53fa8584 0x00300000 ;# DRAM_DQM0
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mww 0x53fa857c 0x00300040 ;# DRAM_SDQS0
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mww 0x53fa8578 0x00300000 ;# DRAM_SDCLK_0
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mww 0x53fa8570 0x00300000 ;# DRAM_SDCLK_1
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mww 0x53fa8574 0x00300000 ;# DRAM_CAS
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mww 0x53fa8588 0x00300000 ;# DRAM_RAS
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mww 0x53fa86f0 0x00300000 ;# GRP_ADDDS
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mww 0x53fa8720 0x00300000 ;# GRP_CTLDS
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mww 0x53fa8564 0x00300040 ;# DRAM_SDODT1
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mww 0x53fa8580 0x00300040 ;# DRAM_SDODT0
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# Initialize DDR2 memory
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mww 0x63fd9088 0x32383535
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mww 0x63fd9090 0x40383538
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mww 0x63fd907c 0x0136014d
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mww 0x63fd9080 0x01510141
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mww 0x63fd9018 0x00011740
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mww 0x63fd9000 0xc3190000
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mww 0x63fd900c 0x555952e3
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mww 0x63fd9010 0xb68e8b63
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mww 0x63fd9014 0x01ff00db
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mww 0x63fd902c 0x000026d2
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mww 0x63fd9030 0x009f0e21
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mww 0x63fd9008 0x12273030
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mww 0x63fd9004 0x0002002d
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mww 0x63fd901c 0x00008032
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mww 0x63fd901c 0x00008033
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mww 0x63fd901c 0x00028031
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mww 0x63fd901c 0x092080b0
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mww 0x63fd901c 0x04008040
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mww 0x63fd901c 0x0000803a
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mww 0x63fd901c 0x0000803b
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mww 0x63fd901c 0x00028039
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mww 0x63fd901c 0x09208138
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mww 0x63fd901c 0x04008048
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mww 0x63fd9020 0x00001800
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mww 0x63fd9040 0x04b80003
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mww 0x63fd9058 0x00022227
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mww 0x63fd901c 0x00000000
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# dap apsel 0
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}
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# vim:filetype=tcl
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