115 lines
4.2 KiB
INI
115 lines
4.2 KiB
INI
# SPDX-License-Identifier: GPL-2.0-or-later
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# Target configuration for the Samsung s3c6410 system on chip
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# Tested on a tiny6410
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# Processor : ARM1176
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# Info : JTAG tap: s3c6410.etb tap/device found: 0x2b900f0f (mfg: 0x787, part: 0xb900, ver: 0x2)
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# Info : JTAG tap: s3c6410.cpu tap/device found: 0x07b76f0f (mfg: 0x787, part: 0x7b76, ver: 0x0)
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source [find target/samsung_s3c6410.cfg]
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proc init_6410 {} {
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halt
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reg cpsr 0x1D3
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arm mcr 15 0 15 2 4 0x70000013
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#-----------------------------------------------
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# Clock and Timer Setting
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#-----------------------------------------------
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mww 0x7e004000 0 ;# WATCHDOG - Disable
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mww 0x7E00F120 0x0003 ;# MEM_SYS_CFG - CS0:8 bit, Mem1:32bit, CS2=NAND
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#mww 0x7E00F120 0x1000 ;# MEM_SYS_CFG - CS0:16bit, Mem1:32bit, CS2=SROMC
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#mww 0x7E00F120 0x1002 ;# MEM_SYS_CFG - CS0:16bit, Mem1:32bit, CS2=OND
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mww 0x7E00F900 0x805e ;# OTHERS - Change SYNCMUX[6] to “1”
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sleep 1000
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mww 0x7E00F900 0x80de ;# OTHERS - Assert SYNCREQ&VICSYNCEN to “1”(rb1004modify)
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sleep 1000 ;# - Others[11:8] to 0xF
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mww 0x7E00F000 0xffff ;# APLL_LOCK - APLL LockTime
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mww 0x7E00F004 0xffff ;# MPLL_LOCK - MPLL LockTime
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mww 0x7E00F020 0x1047310 ;# CLK_DIV0 - ARMCLK:HCLK:PCLK = 1:4:16
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mww 0x7E00F00c 0x81900302 ;# APLL_CON - A:400, P:3, S:2 => 400MHz
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mww 0x7E00F010 0x81900303 ;# MPLL_CON - M:400, P:3, S:3 => 200MHz
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mww 0x7E00F01c 0x3 ;# CLK_SRC - APLL,MPLL Clock Select
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#-----------------------------------------------
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# DRAM initialization
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#-----------------------------------------------
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mww 0x7e001004 0x4 ;# P1MEMCCMD - Enter the config state
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mww 0x7e001010 0x30C ;# P1REFRESH - Refresh Period register (7800ns), 100MHz
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# mww 0x7e001010 0x40e ;# P1REFRESH - Refresh Period register (7800ns), 133MHz
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mww 0x7e001014 0x6 ;# P1CASLAT - CAS Latency = 3
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mww 0x7e001018 0x1 ;# P1T_DQSS
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mww 0x7e00101c 0x2 ;# P1T_MRD
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mww 0x7e001020 0x7 ;# P1T_RAS - 45 ns
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mww 0x7e001024 0xA ;# P1T_RC - 67.5 ns
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mww 0x7e001028 0xC ;# P1T_RCD - 22.5 ns
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mww 0x7e00102C 0x10B ;# P1T_RFC - 80 ns
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mww 0x7e001030 0xC ;# P1T_RP - 22.5 ns
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mww 0x7e001034 0x3 ;# P1T_RRD - 15 ns
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mww 0x7e001038 0x3 ;# P1T_WR - 15 ns
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mww 0x7e00103C 0x2 ;# P1T_WTR
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mww 0x7e001040 0x2 ;# P1T_XP
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mww 0x7e001044 0x11 ;# P1T_XSR - 120 ns
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mww 0x7e001048 0x11 ;# P1T_ESR
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#-----------------------------------------------
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# Memory Configuration Registers
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#-----------------------------------------------
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mww 0x7e00100C 0x00010012 ;# P1MEMCFG - 1 CKE, 1Chip, 4burst, Alw, AP[10],ROW/Column bit
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mww 0x7e00104C 0x0B41 ;# P1MEMCFG2 - Read delay 1 Cycle, mDDR, 32bit, Sync.
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mww 0x7e001200 0x150F0 ;# CHIP_N_CFG - 0x150F0 for 256M, 0x150F8 for 128M
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#-----------------------------------------------
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# Memory Direct Commands
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#-----------------------------------------------
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mww 0x7e001008 0xc0000 ;# Chip0 Direct Command :NOP5
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mww 0x7e001008 0x0 ;# Chip0 Direct Command :PreCharge al
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mww 0x7e001008 0x40000 ;# Chip0 Direct Command :AutoRefresh
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mww 0x7e001008 0x40000 ;# Chip0 Direct Command :AutoRefresh
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mww 0x7e001008 0xA0000 ;# EMRS, DS:Full, PASR:Full
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mww 0x7e001008 0x80032 ;# MRS, CAS3, BL4
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mww 0x7e001004 0x0 ;# Enable DMC1
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}
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proc install_6410_uboot {} {
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# write U-boot magic number
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mww 0x50000000 0x24564236
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mww 0x50000004 0x20764316
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load_image u-boot_nand-ram256.bin 0x50008000 bin
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load_image u-boot_nand-ram256.bin 0x57E00000 bin
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#Kick in
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reg pc 0x57E00000
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resume
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}
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proc init_6410_flash {} {
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halt
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nand probe 0
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nand list
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}
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adapter speed 1000
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adapter srst delay 100
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jtag_ntrst_delay 100
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reset_config trst_and_srst
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gdb_breakpoint_override hard
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targets
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nand device $_CHIPNAME.flash s3c6400 $_CHIPNAME.cpu
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init
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echo " "
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echo " "
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echo "-------------------------------------------------------------------"
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echo "---- The following mini6410/tiny6410 functions are available: ----"
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echo "---- init_6410 - initialize clock, timer, DRAM ----"
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echo "---- init_6410_flash - initializes NAND flash support ----"
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echo "---- install_6410_uboot - copies u-boot image into RAM and ----"
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echo "---- runs it ----"
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echo "-------------------------------------------------------------------"
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echo " "
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echo " "
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