133 lines
5.6 KiB
INI
133 lines
5.6 KiB
INI
# SPDX-License-Identifier: GPL-2.0-or-later
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# This is a stm32h7b3i-dk with a single STM32H7B3LIH6Q chip.
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# https://www.st.com/en/evaluation-tools/stm32h7b3i-dk.html
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#
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# This is for using the onboard STLINK
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source [find interface/stlink.cfg]
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transport select hla_swd
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set CHIPNAME stm32h7b3lih6q
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# enable stmqspi
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if {![info exists OCTOSPI1]} {
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set OCTOSPI1 1
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set OCTOSPI2 0
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}
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source [find target/stm32h7x_dual_bank.cfg]
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reset_config srst_only
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# OCTOSPI initialization
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# octo: 8-line mode
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proc octospi_init { octo } {
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global a b
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mmw 0x58024540 0x000007FF 0 ;# RCC_AHB4ENR |= GPIOAEN-GPIOKEN (enable clocks)
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mmw 0x58024534 0x00284000 0 ;# RCC_AHB3ENR |= IOMNGREN, OSPI2EN, OSPI1EN (enable clocks)
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sleep 1 ;# Wait for clock startup
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mww 0x5200B404 0x03010111 ;# OCTOSPIM_P1CR: assign Port 1 to OCTOSPI1
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mww 0x5200B408 0x00000000 ;# OCTOSPIM_P2CR: disable Port 2
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# PG06: OCSPI1_NCS, PB02: OCSPI1_CLK, PC05: OCSPI1_DQS, PD07: OCSPI1_IO7, PG09: OCSPI1_IO6, PH03: OCSPI1_IO5,
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# PC01: OCSPI1_IO4, PF06: OCSPI1_IO3, PF07: OCSPI1_IO2, PF09: OCSPI1_IO1, PD11: OCSPI1_IO0
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# PB02:AF09:V, PC05:AF10:V, PC01:AF10:V, PD11:AF09:V, PD07:AF10:V, PF09:AF10:V
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# PF07:AF10:V, PF06:AF10:V, PG09:AF09:V, PG06:AF10:V, PH03:AF09:V
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# Port B: PB02:AF09:V
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mmw 0x58020400 0x00000020 0x00000010 ;# MODER
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mmw 0x58020408 0x00000030 0x00000000 ;# OSPEEDR
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mmw 0x5802040C 0x00000000 0x00000030 ;# PUPDR
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mmw 0x58020420 0x00000900 0x00000600 ;# AFRL
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# Port C: PC05:AF10:V, PC01:AF10:V
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mmw 0x58020800 0x00000808 0x00000404 ;# MODER
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mmw 0x58020808 0x00000C0C 0x00000000 ;# OSPEEDR
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mmw 0x5802080C 0x00000000 0x00000C0C ;# PUPDR
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mmw 0x58020820 0x00A000A0 0x00500050 ;# AFRL
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# Port D: PD11:AF09:V, PD07:AF10:V
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mmw 0x58020C00 0x00808000 0x00404000 ;# MODER
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mmw 0x58020C08 0x00C0C000 0x00000000 ;# OSPEEDR
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mmw 0x58020C0C 0x00000000 0x00C0C000 ;# PUPDR
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mmw 0x58020C20 0xA0000000 0x50000000 ;# AFRL
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mmw 0x58020C24 0x00009000 0x00006000 ;# AFRH
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# Port F: PF09:AF10:V, PF07:AF10:V, PF06:AF10:V
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mmw 0x58021400 0x0008A000 0x00045000 ;# MODER
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mmw 0x58021408 0x000CF000 0x00000000 ;# OSPEEDR
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mmw 0x5802140C 0x00000000 0x000CF000 ;# PUPDR
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mmw 0x58021420 0xAA000000 0x55000000 ;# AFRL
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mmw 0x58021424 0x000000A0 0x00000050 ;# AFRH
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# Port G: PG09:AF09:V, PG06:AF10:V
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mmw 0x58021800 0x00082000 0x00041000 ;# MODER
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mmw 0x58021808 0x000C3000 0x00000000 ;# OSPEEDR
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mmw 0x5802180C 0x00000000 0x000C3000 ;# PUPDR
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mmw 0x58021820 0x0A000000 0x05000000 ;# AFRL
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mmw 0x58021824 0x00000090 0x00000060 ;# AFRH
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# Port H: PH03:AF09:V
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mmw 0x58021C00 0x00000080 0x00000040 ;# MODER
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mmw 0x58021C08 0x000000C0 0x00000000 ;# OSPEEDR
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mmw 0x58021C0C 0x00000000 0x000000C0 ;# PUPDR
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mmw 0x58021C20 0x00009000 0x00006000 ;# AFRL
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# OCTOSPI1: memory-mapped 1-line read mode with 4-byte addresses
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mww 0x52005130 0x00001000 ;# OCTOSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full
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mww 0x52005000 0x3040000B ;# OCTOSPI_CR: FMODE=0x1, APMS=1, FTHRES=0, FSEL=0, DQM=0, TCEN=0
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mww 0x52005008 0x01190100 ;# OCTOSPI_DCR1: MTYP=0x1, FSIZE=0x19, CSHT=0x01, CKMODE=0, DLYBYP=0
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mww 0x5200500C 0x00000005 ;# OCTOSPI_DCR2: PRESCALER=5
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mww 0x52005108 0x00000000 ;# OCTOSPI_TCR: SSHIFT=0, DHQC=0, DCYC=0x0
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mww 0x52005100 0x01003101 ;# OCTOSPI_CCR: DMODE=0x1, ABMODE=0x0, ADSIZE=0x3, ADMODE=0x1, ISIZE=0x0, IMODE=0x1
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mww 0x52005110 0x00000013 ;# OCTOSPI_IR: INSTR=READ4B
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flash probe $a ;# load configuration from CR, TCR, CCR, IR register values
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if { $octo == 1 } {
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stmqspi cmd $a 1 0x71 0x00 0x00 0x00 0x00 ;# Read Conf. Reg. 2, addr 0x00000000: DOPI, SOPI bits
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stmqspi cmd $a 0 0x06 ;# Write Enable
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stmqspi cmd $a 1 0x05 ;# Read Status Register
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stmqspi cmd $a 0 0x72 0x00 0x00 0x00 0x00 0x02 ;# Write Conf. Reg. 2, addr 0x00000000: DTR OPI enable
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# OCTOSPI1: memory-mapped 8-line read mode with 4-byte addresses
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mww 0x52005000 0x3040000B ;# OCTOSPI_CR: FMODE=0x3, APMS=1, FTHRES=0, FSEL=0, DQM=0, TCEN=1, EN=1
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mww 0x52005108 0x10000006 ;# OCTOSPI_TCR: SSHIFT=0, DHQC=1, DCYC=0x6
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mww 0x52005100 0x2C003C1C ;# OCTOSPI_CCR: DTR, DMODE=0x4, ABMODE=0x0, ADSIZE=0x3, ADMODE=0x4, ISIZE=0x1, IMODE=0x4
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mww 0x52005110 0x0000EE11 ;# OCTOSPI_IR: INSTR=OCTA DTR Read
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flash probe $a ;# reload configuration from CR, TCR, CCR, IR register values
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stmqspi cmd $a 0 0x06 ;# Write Enable
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stmqspi cmd $a 1 0x05 0x00 0x00 0x00 0x00 ;# Read Status Register (note dummy address in 8-line mode)
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stmqspi cmd $a 0 0x04 ;# Write Disable
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stmqspi cmd $a 1 0x05 0x00 0x00 0x00 0x00 ;# Read Status Register (note dummy address in 8-line mode)
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stmqspi cmd $a 1 0x71 0x00 0x00 0x00 0x00 ;# Read Conf. Reg. 2, addr 0x00000000: DOPI, SOPI bits
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}
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}
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$_CHIPNAME.cpu0 configure -event reset-init {
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global OCTOSPI1
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global OCTOSPI2
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mmw 0x52002000 0x00000004 0x0000000B ;# FLASH_ACR: 4 WS for 192 MHZ HCLK
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mmw 0x58024400 0x00000001 0x00000018 ;# RCC_CR: HSIDIV=1, HSI on
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mmw 0x58024410 0x10000000 0xEE000007 ;# RCC_CFGR: MCO2=system, MCO2PRE=8, HSI as system clock
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mww 0x58024418 0x00000040 ;# RCC_D1CFGR: D1CPRE=1, D1PPRE=2, HPRE=1
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mww 0x5802441C 0x00000440 ;# RCC_D2CFGR: D2PPRE2=2, D2PPRE1=2
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mww 0x58024420 0x00000040 ;# RCC_D3CFGR: D3PPRE=2
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mww 0x58024428 0x00000040 ;# RCC_PPLCKSELR: DIVM3=0, DIVM2=0, DIVM1=4, PLLSRC=HSI
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mmw 0x5802442C 0x0001000C 0x00000002 ;# RCC_PLLCFGR: PLL1RGE=8MHz to 16MHz, PLL1VCOSEL=wide
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mww 0x58024430 0x01070217 ;# RCC_PLL1DIVR: 192 MHz: DIVR1=2, DIVQ=8, DIVP1=2, DIVN1=24
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mmw 0x58024400 0x01000000 0 ;# RCC_CR: PLL1ON=1
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sleep 1
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mmw 0x58024410 0x00000003 0 ;# RCC_CFGR: PLL1 as system clock
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sleep 1
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adapter speed 24000
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if { $OCTOSPI1 } {
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octospi_init 1
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}
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}
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