59 lines
1.9 KiB
INI
59 lines
1.9 KiB
INI
# SPDX-License-Identifier: GPL-2.0-or-later
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# Intel (Altera) Arria10 FPGA SoC
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME arria10
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}
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# ARM CoreSight Debug Access Port (dap HPS)
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if { [info exists DAP_TAPID] } {
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set _DAP_TAPID $DAP_TAPID
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} else {
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set _DAP_TAPID 0x4ba00477
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}
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jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_DAP_TAPID
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# Subsidiary TAP: fpga (tap)
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# See Intel Arria 10 Handbook
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# https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/arria-10/a10_handbook.pdf
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# Intel Arria 10 GX 160 0x02ee20dd
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# Intel Arria 10 GX 220 0x02e220dd
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# Intel Arria 10 GX 270 0x02ee30dd
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# Intel Arria 10 GX 320 0x02e230dd
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# Intel Arria 10 GX 480 0x02e240dd
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# Intel Arria 10 GX 570 0x02ee50dd
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# Intel Arria 10 GX 660 0x02e250dd
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# Intel Arria 10 GX 900 0x02ee60dd
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# Intel Arria 10 GX 1150 0x02e660dd
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# Intel Arria 10 GT 900 0x02e260dd
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# Intel Arria 10 GT 1150 0x02e060dd
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# Intel Arria 10 SX 160 0x02e620dd
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# Intel Arria 10 SX 220 0x02e020dd
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# Intel Arria 10 SX 270 0x02e630dd
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# Intel Arria 10 SX 320 0x02e030dd
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# Intel Arria 10 SX 480 0x02e040dd
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# Intel Arria 10 SX 570 0x02e650dd
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# Intel Arria 10 SX 660 0x02e050dd
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jtag newtap $_CHIPNAME.fpga tap -irlen 10 -expected-id 0x02ee20dd -expected-id 0x02e220dd \
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-expected-id 0x02ee30dd -expected-id 0x02e230dd -expected-id 0x02e240dd \
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-expected-id 0x02ee50dd -expected-id 0x02e250dd -expected-id 0x02ee60dd \
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-expected-id 0x02e660dd -expected-id 0x02e260dd -expected-id 0x02e060dd \
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-expected-id 0x02e620dd -expected-id 0x02e020dd -expected-id 0x02e630dd \
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-expected-id 0x02e030dd -expected-id 0x02e040dd -expected-id 0x02e650dd \
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-expected-id 0x02e050dd
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set _TARGETNAME $_CHIPNAME.cpu
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#
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# Cortex-A9 target
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dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
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target create $_TARGETNAME.0 cortex_a -dap $_CHIPNAME.dap -coreid 0
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target create $_TARGETNAME.1 cortex_a -dap $_CHIPNAME.dap -coreid 1 \
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-defer-examine
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target smp $_TARGETNAME.0 $_TARGETNAME.1
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