129 lines
3.4 KiB
INI
129 lines
3.4 KiB
INI
# SPDX-License-Identifier: GPL-2.0-or-later
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#
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# The ESP32-S3 only supports JTAG.
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transport select jtag
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set CPU_MAX_ADDRESS 0xFFFFFFFF
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source [find bitsbytes.tcl]
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source [find memory.tcl]
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source [find mmr_helpers.tcl]
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME esp32s3
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}
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if { [info exists CPUTAPID] } {
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set _CPUTAPID $CPUTAPID
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} else {
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set _CPUTAPID 0x120034e5
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}
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if { [info exists ESP32_S3_ONLYCPU] } {
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set _ONLYCPU $ESP32_S3_ONLYCPU
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} else {
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set _ONLYCPU 2
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}
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set _CPU0NAME cpu0
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set _CPU1NAME cpu1
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set _TARGETNAME_0 $_CHIPNAME.$_CPU0NAME
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set _TARGETNAME_1 $_CHIPNAME.$_CPU1NAME
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jtag newtap $_CHIPNAME $_CPU0NAME -irlen 5 -expected-id $_CPUTAPID
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if { $_ONLYCPU != 1 } {
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jtag newtap $_CHIPNAME $_CPU1NAME -irlen 5 -expected-id $_CPUTAPID
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} else {
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jtag newtap $_CHIPNAME $_CPU1NAME -irlen 5 -disable -expected-id $_CPUTAPID
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}
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proc esp32s3_memprot_is_enabled { } {
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# SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0_REG
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if { [get_mmr_bit 0x600C10C0 0] != 0 } {
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return 1
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}
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# SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_0_REG
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if { [get_mmr_bit 0x600C1124 0] != 0 } {
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return 1
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}
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# SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_0_REG
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if { [get_mmr_bit 0x600C11D0 0] != 0 } {
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return 1
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}
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# IRAM0, SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_0_REG
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if { [get_mmr_bit 0x600C10D8 0] != 0 } {
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return 1
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}
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# DRAM0, SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_0_REG
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if { [get_mmr_bit 0x600C10FC 0] != 0 } {
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return 1
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}
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# SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_0_REG
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if { [get_mmr_bit 0x600C10E4 0] != 0 } {
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return 1
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}
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# SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_0_REG
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if { [get_mmr_bit 0x600C10F0 0] != 0 } {
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return 1
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}
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# SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_0_REG
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if { [get_mmr_bit 0x600C1104 0] != 0 } {
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return 1
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}
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# SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_0_REG
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if { [get_mmr_bit 0x600C1114 0] != 0 } {
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return 1
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}
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# SENSITIVE_CORE_0_PIF_PMS_MONITOR_0_REG
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if { [get_mmr_bit 0x600C119C 0] != 0 } {
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return 1
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}
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# SENSITIVE_CORE_1_PIF_PMS_MONITOR_0_REG
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if { [get_mmr_bit 0x600C1248 0] != 0 } {
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return 1
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}
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return 0
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}
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# PRO-CPU
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target create $_TARGETNAME_0 $_CHIPNAME -endian little -chain-position $_TARGETNAME_0 -coreid 0
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# APP-CPU
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if { $_ONLYCPU != 1 } {
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target create $_TARGETNAME_1 $_CHIPNAME -endian little -chain-position $_TARGETNAME_1 -coreid 1
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target smp $_TARGETNAME_0 $_TARGETNAME_1
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}
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$_TARGETNAME_0 xtensa maskisr on
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$_TARGETNAME_0 xtensa smpbreak BreakIn BreakOut
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$_TARGETNAME_0 configure -event gdb-attach {
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$_TARGETNAME_0 xtensa smpbreak BreakIn BreakOut
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# necessary to auto-probe flash bank when GDB is connected and generate proper memory map
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halt 1000
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if { [esp32s3_memprot_is_enabled] } {
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# 'reset halt' to disable memory protection and allow flasher to work correctly
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echo "Memory protection is enabled. Reset target to disable it..."
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reset halt
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}
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}
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$_TARGETNAME_0 configure -event reset-assert-post { soft_reset_halt }
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if { $_ONLYCPU != 1 } {
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$_TARGETNAME_1 configure -event gdb-attach {
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$_TARGETNAME_1 xtensa smpbreak BreakIn BreakOut
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# necessary to auto-probe flash bank when GDB is connected
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halt 1000
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if { [esp32s3_memprot_is_enabled] } {
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# 'reset halt' to disable memory protection and allow flasher to work correctly
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echo "Memory protection is enabled. Reset target to disable it..."
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reset halt
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}
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}
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$_TARGETNAME_1 configure -event reset-assert-post { soft_reset_halt }
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}
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gdb_breakpoint_override hard
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source [find target/xtensa-core-esp32s3.cfg]
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