75 lines
1.6 KiB
INI
75 lines
1.6 KiB
INI
# SPDX-License-Identifier: GPL-2.0-or-later
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source [find target/swj-dp.tcl]
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adapter speed 500
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME lpc4350
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}
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#
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# M4 JTAG mode TAP
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#
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if { [info exists M4_JTAG_TAPID] } {
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set _M4_JTAG_TAPID $M4_JTAG_TAPID
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} else {
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set _M4_JTAG_TAPID 0x4ba00477
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}
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#
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# M4 SWD mode TAP
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#
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if { [info exists M4_SWD_TAPID] } {
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set _M4_SWD_TAPID $M4_SWD_TAPID
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} else {
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set _M4_SWD_TAPID 0x2ba01477
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}
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if { [using_jtag] } {
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set _M4_TAPID $_M4_JTAG_TAPID
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} {
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set _M4_TAPID $_M4_SWD_TAPID
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}
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#
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# M0 TAP
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#
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if { [info exists M0_JTAG_TAPID] } {
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set _M0_JTAG_TAPID $M0_JTAG_TAPID
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} else {
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set _M0_JTAG_TAPID 0x0ba01477
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}
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swj_newdap $_CHIPNAME m4 -irlen 4 -ircapture 0x1 -irmask 0xf \
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-expected-id $_M4_TAPID
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dap create $_CHIPNAME.m4.dap -chain-position $_CHIPNAME.m4
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target create $_CHIPNAME.m4 cortex_m -dap $_CHIPNAME.m4.dap
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if { [using_jtag] } {
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swj_newdap $_CHIPNAME m0 -irlen 4 -ircapture 0x1 -irmask 0xf \
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-expected-id $_M0_JTAG_TAPID
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dap create $_CHIPNAME.m0.dap -chain-position $_CHIPNAME.m0
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target create $_CHIPNAME.m0 cortex_m -dap $_CHIPNAME.m0.dap
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}
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# LPC4350 has 96+32 KB SRAM
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if { [info exists WORKAREASIZE] } {
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set _WORKAREASIZE $WORKAREASIZE
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} else {
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set _WORKAREASIZE 0x20000
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}
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$_CHIPNAME.m4 configure -work-area-phys 0x10000000 \
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-work-area-size $_WORKAREASIZE -work-area-backup 0
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if {![using_hla]} {
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# on this CPU we should use VECTRESET to perform a soft reset and
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# manually reset the periphery
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# SRST or SYSRESETREQ disable the debug interface for the time of
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# the reset and will not fit our requirements for a consistent debug
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# session
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cortex_m reset_config vectreset
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}
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