84 lines
3.4 KiB
INI
84 lines
3.4 KiB
INI
# SPDX-License-Identifier: GPL-2.0-or-later
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# NXP LPC8Nxx NHS31xx Cortex-M0+ with 8kB SRAM
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# Copyright (C) 2018 by Jean-Christian de Rivaz
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# Based on NXP proposal https://community.nxp.com/message/1011149
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# Many thanks to Dries Moors from NXP support.
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# SWD only transport
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source [find target/swj-dp.tcl]
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source [find mem_helper.tcl]
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME lpc8nxx
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}
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swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id 0
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dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap
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if {![using_hla]} {
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# If srst is not fitted use SYSRESETREQ to perform a soft reset
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cortex_m reset_config sysresetreq
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}
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adapter srst delay 100
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$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size 0x1ff0 -work-area-backup 0
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flash bank $_CHIPNAME.flash lpc2000 0x0 0x7800 0 0 $_TARGETNAME lpc800 500
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echo "*********************************************************************************"
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echo "* !!!!! IMPORTANT NOTICE FOR LPC8Nxx and NHS31xx CHIPS !!!!!"
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echo "* When this IC is in power-off or peep power down mode, the SWD HW block is also"
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echo "* unpowered. These modes can be entered by firmware. The default firmware image"
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echo "* (flashed in production) makes use of this. Best is to avoid these power modes"
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echo "* during development, and only later add them when the functionality is complete."
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echo "* Hardware reset or NFC field are the only ways to connect in case the SWD is"
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echo "* powered off. OpenOCD can do a hardware reset if you wire the adapter SRST"
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echo "* signal to the chip RESETN pin and add the following in your configuration:"
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echo "* reset_config srst_only; flash init; catch init; reset"
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echo "* But if the actual firmware immediately set the power down mode after reset,"
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echo "* OpenOCD might be not fast enough to halt the CPU before the SWD lost power. In"
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echo "* that case the only solution is to apply a NFC field to keep the SWD powered."
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echo "*********************************************************************************"
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# Using soft-reset 'reset_config none' is strongly discouraged.
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# RESETN sets the system clock to 500 kHz. Unlike soft-reset does not.
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# Set the system clock to 500 kHz before reset to simulate the functionality of hw reset.
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#
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proc set_sysclk_500khz {} {
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set SYSCLKCTRL 0x40048020
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set SYSCLKUEN 0x40048024
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mww $SYSCLKUEN 0
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mmw $SYSCLKCTRL 0x8 0xe
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mww $SYSCLKUEN 1
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echo "Notice: sysclock set to 500kHz."
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}
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# Do not remap the ARM interrupt vectors to anything but the beginning of the flash.
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# Table System memory remap register (SYSMEMREMAP, address 0x4004 8000) bit description
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# Bit Symbol Value Description
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# 0 map - interrupt vector remap. 0 after boot.
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# 0 interrupt vector reside in Flash
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# 1 interrupt vector reside in SRAM
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# 5:1 offset - system memory remap offset. 00000b after boot.
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# 00000b interrupt vectors in flash or remapped to SRAM but no offset
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# 00001b -
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# 00111b interrupt vectors offset in flash or SRAM to 1K word segment
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# 01000b -
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# 11111b interrupt vectors offset in flash to 1K word segment 8 to 31
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# 31:6 reserved
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#
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proc set_no_remap {} {
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mww 0x40048000 0x00
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echo "Notice: interrupt vector set to no remap."
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}
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$_TARGETNAME configure -event reset-init {
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set_sysclk_500khz
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set_no_remap
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}
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