34 lines
870 B
Tcl
34 lines
870 B
Tcl
# SPDX-License-Identifier: GPL-2.0-or-later
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# Copyright (C) 2014-2015,2020 Synopsys, Inc.
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# Anton Kolesov <anton.kolesov@synopsys.com>
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# Didin Evgeniy <didin@synopsys.com>
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#
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# Xilinx Spartan-6 XC6SLX45 FPGA on EM Starter Kit v1.
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# Xilinx Spartan-6 XC6SLX150 FPGA on EM Starter Kit v2.
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#
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source [find cpu/arc/em.tcl]
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set _CHIPNAME arc-em
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set _TARGETNAME $_CHIPNAME.cpu
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# EM SK IDENTITY is 0x200444b1
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# EM SK v2 IDENTITY is 0x200044b1
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jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -expected-id 0x200444b1 \
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-expected-id 0x200044b1
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set _coreid 0
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set _dbgbase [expr {0x00000000 | ($_coreid << 13)}]
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target create $_TARGETNAME arcv2 -chain-position $_TARGETNAME \
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-coreid 0 -dbgbase $_dbgbase -endian little
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# There is no SRST, so do a software reset
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$_TARGETNAME configure -event reset-assert "arc_em_reset $_TARGETNAME"
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arc_em_init_regs
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# vim:ft=tcl
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