98 lines
2.5 KiB
INI
98 lines
2.5 KiB
INI
# SPDX-License-Identifier: GPL-2.0-or-later
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# script for stm32f0x family
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#
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# stm32 devices support SWD transports only.
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#
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source [find target/swj-dp.tcl]
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source [find mem_helper.tcl]
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME stm32f0x
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}
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set _ENDIAN little
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# Work-area is a space in RAM used for flash programming
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# By default use 4kB
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if { [info exists WORKAREASIZE] } {
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set _WORKAREASIZE $WORKAREASIZE
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} else {
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set _WORKAREASIZE 0x1000
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}
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# Allow overriding the Flash bank size
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if { [info exists FLASH_SIZE] } {
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set _FLASH_SIZE $FLASH_SIZE
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} else {
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# autodetect size
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set _FLASH_SIZE 0
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}
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#jtag scan chain
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if { [info exists CPUTAPID] } {
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set _CPUTAPID $CPUTAPID
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} else {
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# See STM Document RM0091
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# Section 29.5.3
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set _CPUTAPID 0x0bb11477
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}
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swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
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dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
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$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
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# flash size will be probed
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set _FLASHNAME $_CHIPNAME.flash
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flash bank $_FLASHNAME stm32f1x 0x08000000 $_FLASH_SIZE 0 0 $_TARGETNAME
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# adapter speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
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adapter speed 1000
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adapter srst delay 100
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reset_config srst_nogate
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if {![using_hla]} {
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# if srst is not fitted use SYSRESETREQ to
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# perform a soft reset
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cortex_m reset_config sysresetreq
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}
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proc stm32f0x_default_reset_start {} {
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# Reset clock is HSI (8 MHz)
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adapter speed 1000
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}
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proc stm32f0x_default_examine_end {} {
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# Enable debug during low power modes (uses more power)
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mmw 0x40015804 0x00000006 0 ;# DBGMCU_CR |= DBG_STANDBY | DBG_STOP
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# Stop watchdog counters during halt
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mmw 0x40015808 0x00001800 0 ;# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
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}
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proc stm32f0x_default_reset_init {} {
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# Configure PLL to boost clock to HSI x 6 (48 MHz)
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mww 0x40021004 0x00100000 ;# RCC_CFGR = PLLMUL[2]
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mmw 0x40021000 0x01000000 0 ;# RCC_CR[31:16] |= PLLON
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mww 0x40022000 0x00000011 ;# FLASH_ACR = PRFTBE | LATENCY[0]
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sleep 10 ;# Wait for PLL to lock
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mmw 0x40021004 0x00000002 0 ;# RCC_CFGR |= SW[1]
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# Boost JTAG frequency
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adapter speed 8000
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}
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# Default hooks
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$_TARGETNAME configure -event examine-end { stm32f0x_default_examine_end }
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$_TARGETNAME configure -event reset-start { stm32f0x_default_reset_start }
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$_TARGETNAME configure -event reset-init { stm32f0x_default_reset_init }
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