94 lines
2.2 KiB
INI
94 lines
2.2 KiB
INI
# SPDX-License-Identifier: GPL-2.0-or-later
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#
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# M0+ devices only have SW-DP, but swj-dp code works, just don't
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# set any jtag related features
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#
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source [find target/swj-dp.tcl]
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source [find mem_helper.tcl]
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME stm32l0
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}
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set _ENDIAN little
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# Work-area is a space in RAM used for flash programming
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# By default use 2kB (max ram on smallest part)
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if { [info exists WORKAREASIZE] } {
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set _WORKAREASIZE $WORKAREASIZE
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} else {
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set _WORKAREASIZE 0x800
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}
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# JTAG speed should be <= F_CPU/6.
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# F_CPU after reset is ~2MHz, so use F_JTAG max = 333kHz
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adapter speed 300
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adapter srst delay 100
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if { [info exists CPUTAPID] } {
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set _CPUTAPID $CPUTAPID
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} else {
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# Arm, m0+, non-multidrop.
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# http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.faqs/ka16088.html
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set _CPUTAPID 0x0bc11477
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}
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swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
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dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
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$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
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# flash size will be probed
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set _FLASHNAME $_CHIPNAME.flash
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flash bank $_FLASHNAME stm32lx 0x08000000 0 0 0 $_TARGETNAME
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reset_config srst_nogate
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if {![using_hla]} {
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# if srst is not fitted use SYSRESETREQ to
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# perform a soft reset
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cortex_m reset_config sysresetreq
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}
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proc stm32l0_enable_HSI16 {} {
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# Enable HSI16 as clock source
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echo "STM32L0: Enabling HSI16"
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# Set HSI16ON in RCC_CR (leave MSI enabled)
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mmw 0x40021000 0x00000101 0
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# Set HSI16 as SYSCLK (RCC_CFGR)
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mmw 0x4002100c 0x00000001 0
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# Wait until System clock switches to HSI16
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while { ([ mrw 0x4002100c ] & 0x0c) != 0x04 } { }
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# Increase speed
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adapter speed 2500
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}
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$_TARGETNAME configure -event reset-init {
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stm32l0_enable_HSI16
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}
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$_TARGETNAME configure -event reset-start {
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adapter speed 300
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}
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$_TARGETNAME configure -event examine-end {
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# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
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mmw 0x40015804 0x00000007 0
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# Stop watchdog counters during halt
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# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
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mmw 0x40015808 0x00001800 0
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}
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