openocd/tcl/target/vd_xtensa_jtag.cfg

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INI

# SPDX-License-Identifier: GPL-2.0-or-later
# Cadence virtual debug interface
# for Palladium emulation systems
#
# TODO: Enable backdoor memory access
# set _MEMSTART 0x00000000
# set _MEMSIZE 0x100000
# BFM hierarchical path and input clk period
vdebug bfm_path dut_top.JTAG 10ns
# DMA Memories to access backdoor (up to 4)
# vdebug mem_path tbench.u_mcu.u_sys.u_itcm_ram.Mem $_MEMSTART $_MEMSIZE
# Create Xtensa target first
source [find target/xtensa.cfg]
# Configure Xtensa core parameters next
# Generate [xtensa-core-XXX.cfg] via "xt-gdb --dump-oocd-config"
# register target
proc vdebug_examine_end {} {
# vdebug register_target
}
# Default hooks
$_TARGETNAME configure -event examine-end { vdebug_examine_end }