015bf55944
Add comments to assembly flash loader for STM32. Add tiny improvement in size of the algorithm (40 vs 48 bytes) and tiny speed improvement (~1.5%, as time is wasted on waiting for end of operation anyway). Signed-off-by: Freddie Chopin <freddie_chopin@op.pl>
1363 lines
34 KiB
C
1363 lines
34 KiB
C
/***************************************************************************
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* Copyright (C) 2005 by Dominic Rath *
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* Dominic.Rath@gmx.de *
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* *
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* Copyright (C) 2008 by Spencer Oliver *
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* spen@spen-soft.co.uk *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, write to the *
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* Free Software Foundation, Inc., *
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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***************************************************************************/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include "imp.h"
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#include "stm32x.h"
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#include <helper/binarybuffer.h>
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#include <target/algorithm.h>
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#include <target/armv7m.h>
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static int stm32x_mass_erase(struct flash_bank *bank);
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/* flash bank stm32x <base> <size> 0 0 <target#>
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*/
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FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command)
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{
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struct stm32x_flash_bank *stm32x_info;
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if (CMD_ARGC < 6)
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{
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LOG_WARNING("incomplete flash_bank stm32x configuration");
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return ERROR_FLASH_BANK_INVALID;
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}
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stm32x_info = malloc(sizeof(struct stm32x_flash_bank));
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bank->driver_priv = stm32x_info;
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stm32x_info->write_algorithm = NULL;
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stm32x_info->probed = 0;
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return ERROR_OK;
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}
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static int stm32x_get_flash_status(struct flash_bank *bank, uint32_t *status)
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{
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struct target *target = bank->target;
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return target_read_u32(target, STM32_FLASH_SR, status);
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}
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static int stm32x_wait_status_busy(struct flash_bank *bank, int timeout)
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{
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struct target *target = bank->target;
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uint32_t status;
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int retval = ERROR_OK;
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/* wait for busy to clear */
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for (;;)
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{
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retval = stm32x_get_flash_status(bank, &status);
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if (retval != ERROR_OK)
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return retval;
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LOG_DEBUG("status: 0x%" PRIx32 "", status);
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if ((status & FLASH_BSY) == 0)
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break;
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if (timeout-- <= 0)
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{
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LOG_ERROR("timed out waiting for flash");
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return ERROR_FAIL;
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}
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alive_sleep(1);
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}
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if (status & FLASH_WRPRTERR)
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{
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LOG_ERROR("stm32x device protected");
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retval = ERROR_FAIL;
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}
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if (status & FLASH_PGERR)
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{
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LOG_ERROR("stm32x device programming failed");
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retval = ERROR_FAIL;
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}
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/* Clear but report errors */
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if (status & (FLASH_WRPRTERR | FLASH_PGERR))
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{
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/* If this operation fails, we ignore it and report the original
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* retval
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*/
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target_write_u32(target, STM32_FLASH_SR, FLASH_WRPRTERR | FLASH_PGERR);
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}
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return retval;
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}
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static int stm32x_read_options(struct flash_bank *bank)
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{
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uint32_t optiondata;
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struct stm32x_flash_bank *stm32x_info = NULL;
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struct target *target = bank->target;
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stm32x_info = bank->driver_priv;
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/* read current option bytes */
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int retval = target_read_u32(target, STM32_FLASH_OBR, &optiondata);
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if (retval != ERROR_OK)
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return retval;
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stm32x_info->option_bytes.user_options = (uint16_t)0xFFF8 | ((optiondata >> 2) & 0x07);
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stm32x_info->option_bytes.RDP = (optiondata & (1 << OPT_READOUT)) ? 0xFFFF : 0x5AA5;
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if (optiondata & (1 << OPT_READOUT))
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LOG_INFO("Device Security Bit Set");
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/* each bit refers to a 4bank protection */
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retval = target_read_u32(target, STM32_FLASH_WRPR, &optiondata);
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if (retval != ERROR_OK)
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return retval;
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stm32x_info->option_bytes.protection[0] = (uint16_t)optiondata;
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stm32x_info->option_bytes.protection[1] = (uint16_t)(optiondata >> 8);
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stm32x_info->option_bytes.protection[2] = (uint16_t)(optiondata >> 16);
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stm32x_info->option_bytes.protection[3] = (uint16_t)(optiondata >> 24);
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return ERROR_OK;
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}
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static int stm32x_erase_options(struct flash_bank *bank)
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{
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struct stm32x_flash_bank *stm32x_info = NULL;
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struct target *target = bank->target;
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stm32x_info = bank->driver_priv;
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/* read current options */
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stm32x_read_options(bank);
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/* unlock flash registers */
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int retval = target_write_u32(target, STM32_FLASH_KEYR, KEY1);
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if (retval != ERROR_OK)
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return retval;
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retval = target_write_u32(target, STM32_FLASH_KEYR, KEY2);
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if (retval != ERROR_OK)
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return retval;
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/* unlock option flash registers */
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retval = target_write_u32(target, STM32_FLASH_OPTKEYR, KEY1);
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if (retval != ERROR_OK)
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return retval;
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retval = target_write_u32(target, STM32_FLASH_OPTKEYR, KEY2);
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if (retval != ERROR_OK)
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return retval;
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/* erase option bytes */
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retval = target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER | FLASH_OPTWRE);
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if (retval != ERROR_OK)
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return retval;
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retval = target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER | FLASH_STRT | FLASH_OPTWRE);
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if (retval != ERROR_OK)
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return retval;
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retval = stm32x_wait_status_busy(bank, 10);
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if (retval != ERROR_OK)
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return retval;
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/* clear readout protection and complementary option bytes
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* this will also force a device unlock if set */
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stm32x_info->option_bytes.RDP = 0x5AA5;
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return ERROR_OK;
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}
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static int stm32x_write_options(struct flash_bank *bank)
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{
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struct stm32x_flash_bank *stm32x_info = NULL;
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struct target *target = bank->target;
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stm32x_info = bank->driver_priv;
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/* unlock flash registers */
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int retval = target_write_u32(target, STM32_FLASH_KEYR, KEY1);
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if (retval != ERROR_OK)
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return retval;
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retval = target_write_u32(target, STM32_FLASH_KEYR, KEY2);
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if (retval != ERROR_OK)
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return retval;
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/* unlock option flash registers */
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retval = target_write_u32(target, STM32_FLASH_OPTKEYR, KEY1);
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if (retval != ERROR_OK)
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return retval;
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retval = target_write_u32(target, STM32_FLASH_OPTKEYR, KEY2);
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if (retval != ERROR_OK)
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return retval;
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/* program option bytes */
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retval = target_write_u32(target, STM32_FLASH_CR, FLASH_OPTPG | FLASH_OPTWRE);
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if (retval != ERROR_OK)
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return retval;
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/* write user option byte */
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retval = target_write_u16(target, STM32_OB_USER, stm32x_info->option_bytes.user_options);
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if (retval != ERROR_OK)
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return retval;
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retval = stm32x_wait_status_busy(bank, 10);
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if (retval != ERROR_OK)
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return retval;
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/* write protection byte 1 */
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retval = target_write_u16(target, STM32_OB_WRP0, stm32x_info->option_bytes.protection[0]);
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if (retval != ERROR_OK)
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return retval;
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retval = stm32x_wait_status_busy(bank, 10);
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if (retval != ERROR_OK)
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return retval;
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/* write protection byte 2 */
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retval = target_write_u16(target, STM32_OB_WRP1, stm32x_info->option_bytes.protection[1]);
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if (retval != ERROR_OK)
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return retval;
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retval = stm32x_wait_status_busy(bank, 10);
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if (retval != ERROR_OK)
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return retval;
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/* write protection byte 3 */
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retval = target_write_u16(target, STM32_OB_WRP2, stm32x_info->option_bytes.protection[2]);
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if (retval != ERROR_OK)
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return retval;
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retval = stm32x_wait_status_busy(bank, 10);
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if (retval != ERROR_OK)
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return retval;
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/* write protection byte 4 */
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retval = target_write_u16(target, STM32_OB_WRP3, stm32x_info->option_bytes.protection[3]);
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if (retval != ERROR_OK)
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return retval;
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retval = stm32x_wait_status_busy(bank, 10);
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if (retval != ERROR_OK)
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return retval;
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/* write readout protection bit */
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retval = target_write_u16(target, STM32_OB_RDP, stm32x_info->option_bytes.RDP);
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if (retval != ERROR_OK)
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return retval;
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retval = stm32x_wait_status_busy(bank, 10);
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if (retval != ERROR_OK)
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return retval;
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retval = target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
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if (retval != ERROR_OK)
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return retval;
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return ERROR_OK;
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}
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static int stm32x_protect_check(struct flash_bank *bank)
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{
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struct target *target = bank->target;
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struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
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uint32_t protection;
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int i, s;
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int num_bits;
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int set;
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if (target->state != TARGET_HALTED)
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{
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LOG_ERROR("Target not halted");
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return ERROR_TARGET_NOT_HALTED;
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}
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/* medium density - each bit refers to a 4bank protection
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* high density - each bit refers to a 2bank protection */
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int retval = target_read_u32(target, STM32_FLASH_WRPR, &protection);
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if (retval != ERROR_OK)
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return retval;
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/* medium density - each protection bit is for 4 * 1K pages
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* high density - each protection bit is for 2 * 2K pages */
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num_bits = (bank->num_sectors / stm32x_info->ppage_size);
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if (stm32x_info->ppage_size == 2)
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{
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/* high density flash/connectivity line protection */
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set = 1;
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if (protection & (1 << 31))
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set = 0;
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/* bit 31 controls sector 62 - 255 protection for high density
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* bit 31 controls sector 62 - 127 protection for connectivity line */
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for (s = 62; s < bank->num_sectors; s++)
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{
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bank->sectors[s].is_protected = set;
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}
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if (bank->num_sectors > 61)
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num_bits = 31;
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for (i = 0; i < num_bits; i++)
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{
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set = 1;
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if (protection & (1 << i))
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set = 0;
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for (s = 0; s < stm32x_info->ppage_size; s++)
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bank->sectors[(i * stm32x_info->ppage_size) + s].is_protected = set;
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}
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}
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else
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{
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/* low/medium density flash protection */
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for (i = 0; i < num_bits; i++)
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{
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set = 1;
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if (protection & (1 << i))
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set = 0;
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for (s = 0; s < stm32x_info->ppage_size; s++)
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bank->sectors[(i * stm32x_info->ppage_size) + s].is_protected = set;
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}
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}
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return ERROR_OK;
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}
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static int stm32x_erase(struct flash_bank *bank, int first, int last)
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{
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struct target *target = bank->target;
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int i;
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if (bank->target->state != TARGET_HALTED)
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{
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LOG_ERROR("Target not halted");
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return ERROR_TARGET_NOT_HALTED;
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}
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if ((first == 0) && (last == (bank->num_sectors - 1)))
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{
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return stm32x_mass_erase(bank);
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}
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/* unlock flash registers */
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int retval = target_write_u32(target, STM32_FLASH_KEYR, KEY1);
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if (retval != ERROR_OK)
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return retval;
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retval = target_write_u32(target, STM32_FLASH_KEYR, KEY2);
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if (retval != ERROR_OK)
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return retval;
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for (i = first; i <= last; i++)
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{
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retval = target_write_u32(target, STM32_FLASH_CR, FLASH_PER);
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if (retval != ERROR_OK)
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return retval;
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retval = target_write_u32(target, STM32_FLASH_AR, bank->base + bank->sectors[i].offset);
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if (retval != ERROR_OK)
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return retval;
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retval = target_write_u32(target, STM32_FLASH_CR, FLASH_PER | FLASH_STRT);
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if (retval != ERROR_OK)
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return retval;
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retval = stm32x_wait_status_busy(bank, 100);
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if (retval != ERROR_OK)
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return retval;
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bank->sectors[i].is_erased = 1;
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}
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retval = target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
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if (retval != ERROR_OK)
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return retval;
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return ERROR_OK;
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}
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static int stm32x_protect(struct flash_bank *bank, int set, int first, int last)
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{
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struct stm32x_flash_bank *stm32x_info = NULL;
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struct target *target = bank->target;
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uint16_t prot_reg[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};
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int i, reg, bit;
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int status;
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uint32_t protection;
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stm32x_info = bank->driver_priv;
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if (target->state != TARGET_HALTED)
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{
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LOG_ERROR("Target not halted");
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return ERROR_TARGET_NOT_HALTED;
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}
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if ((first && (first % stm32x_info->ppage_size)) || ((last + 1) &&
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(last + 1) % stm32x_info->ppage_size))
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{
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LOG_WARNING("Error: start and end sectors must be on a %d sector boundary",
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stm32x_info->ppage_size);
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return ERROR_FLASH_SECTOR_INVALID;
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}
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/* medium density - each bit refers to a 4bank protection
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* high density - each bit refers to a 2bank protection */
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int retval = target_read_u32(target, STM32_FLASH_WRPR, &protection);
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if (retval != ERROR_OK)
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return retval;
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prot_reg[0] = (uint16_t)protection;
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prot_reg[1] = (uint16_t)(protection >> 8);
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prot_reg[2] = (uint16_t)(protection >> 16);
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prot_reg[3] = (uint16_t)(protection >> 24);
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if (stm32x_info->ppage_size == 2)
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{
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/* high density flash */
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/* bit 7 controls sector 62 - 255 protection */
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if (last > 61)
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{
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if (set)
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prot_reg[3] &= ~(1 << 7);
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else
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prot_reg[3] |= (1 << 7);
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}
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if (first > 61)
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first = 62;
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if (last > 61)
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last = 61;
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for (i = first; i <= last; i++)
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{
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reg = (i / stm32x_info->ppage_size) / 8;
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bit = (i / stm32x_info->ppage_size) - (reg * 8);
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if (set)
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prot_reg[reg] &= ~(1 << bit);
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else
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prot_reg[reg] |= (1 << bit);
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}
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}
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else
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{
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/* medium density flash */
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for (i = first; i <= last; i++)
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{
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reg = (i / stm32x_info->ppage_size) / 8;
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bit = (i / stm32x_info->ppage_size) - (reg * 8);
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if (set)
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prot_reg[reg] &= ~(1 << bit);
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else
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prot_reg[reg] |= (1 << bit);
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}
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}
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if ((status = stm32x_erase_options(bank)) != ERROR_OK)
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return status;
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stm32x_info->option_bytes.protection[0] = prot_reg[0];
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stm32x_info->option_bytes.protection[1] = prot_reg[1];
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stm32x_info->option_bytes.protection[2] = prot_reg[2];
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stm32x_info->option_bytes.protection[3] = prot_reg[3];
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return stm32x_write_options(bank);
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}
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static int stm32x_write_block(struct flash_bank *bank, uint8_t *buffer,
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uint32_t offset, uint32_t count)
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{
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struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
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struct target *target = bank->target;
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uint32_t buffer_size = 16384;
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struct working_area *source;
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uint32_t address = bank->base + offset;
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struct reg_param reg_params[4];
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struct armv7m_algorithm armv7m_info;
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int retval = ERROR_OK;
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/* see contib/loaders/flash/stm32x.s for src */
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|
|
static const uint8_t stm32x_flash_write_code[] = {
|
|
/* #define STM32_FLASH_CR_OFFSET 0x10 */
|
|
/* #define STM32_FLASH_SR_OFFSET 0x0C */
|
|
/* write: */
|
|
0xdf, 0xf8, 0x20, 0x40, /* ldr r4, STM32_FLASH_BASE */
|
|
/* write_half_word: */
|
|
0x01, 0x23, /* movs r3, #0x01 */
|
|
0x23, 0x61, /* str r3, [r4, #STM32_FLASH_CR_OFFSET] */
|
|
0x30, 0xf8, 0x02, 0x3b, /* ldrh r3, [r0], #0x02 */
|
|
0x21, 0xf8, 0x02, 0x3b, /* strh r3, [r1], #0x02 */
|
|
/* busy: */
|
|
0xe3, 0x68, /* ldr r3, [r4, #STM32_FLASH_SR_OFFSET] */
|
|
0x13, 0xf0, 0x01, 0x0f, /* tst r3, #0x01 */
|
|
0xfb, 0xd0, /* beq busy */
|
|
0x13, 0xf0, 0x14, 0x0f, /* tst r3, #0x14 */
|
|
0x01, 0xd1, /* bne exit */
|
|
0x01, 0x3a, /* subs r2, r2, #0x01 */
|
|
0xf0, 0xd1, /* bne write_half_word */
|
|
/* exit: */
|
|
0x00, 0xbe, /* bkpt #0x00 */
|
|
0x00, 0x20, 0x02, 0x40, /* STM32_FLASH_BASE: .word 0x40022000 */
|
|
};
|
|
|
|
/* flash write code */
|
|
if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code),
|
|
&stm32x_info->write_algorithm) != ERROR_OK)
|
|
{
|
|
LOG_WARNING("no working area available, can't do block memory writes");
|
|
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
|
|
};
|
|
|
|
if ((retval = target_write_buffer(target, stm32x_info->write_algorithm->address,
|
|
sizeof(stm32x_flash_write_code),
|
|
(uint8_t*)stm32x_flash_write_code)) != ERROR_OK)
|
|
return retval;
|
|
|
|
/* memory buffer */
|
|
while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK)
|
|
{
|
|
buffer_size /= 2;
|
|
if (buffer_size <= 256)
|
|
{
|
|
/* if we already allocated the writing code, but failed to get a
|
|
* buffer, free the algorithm */
|
|
if (stm32x_info->write_algorithm)
|
|
target_free_working_area(target, stm32x_info->write_algorithm);
|
|
|
|
LOG_WARNING("no large enough working area available, can't do block memory writes");
|
|
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
|
|
}
|
|
};
|
|
|
|
armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
|
|
armv7m_info.core_mode = ARMV7M_MODE_ANY;
|
|
|
|
init_reg_param(®_params[0], "r0", 32, PARAM_OUT);
|
|
init_reg_param(®_params[1], "r1", 32, PARAM_OUT);
|
|
init_reg_param(®_params[2], "r2", 32, PARAM_OUT);
|
|
init_reg_param(®_params[3], "r3", 32, PARAM_IN);
|
|
|
|
while (count > 0)
|
|
{
|
|
uint32_t thisrun_count = (count > (buffer_size / 2)) ?
|
|
(buffer_size / 2) : count;
|
|
|
|
if ((retval = target_write_buffer(target, source->address,
|
|
thisrun_count * 2, buffer)) != ERROR_OK)
|
|
break;
|
|
|
|
buf_set_u32(reg_params[0].value, 0, 32, source->address);
|
|
buf_set_u32(reg_params[1].value, 0, 32, address);
|
|
buf_set_u32(reg_params[2].value, 0, 32, thisrun_count);
|
|
|
|
if ((retval = target_run_algorithm(target, 0, NULL, 4, reg_params,
|
|
stm32x_info->write_algorithm->address,
|
|
0,
|
|
10000, &armv7m_info)) != ERROR_OK)
|
|
{
|
|
LOG_ERROR("error executing stm32x flash write algorithm");
|
|
break;
|
|
}
|
|
|
|
if (buf_get_u32(reg_params[3].value, 0, 32) & FLASH_PGERR)
|
|
{
|
|
LOG_ERROR("flash memory not erased before writing");
|
|
/* Clear but report errors */
|
|
target_write_u32(target, STM32_FLASH_SR, FLASH_PGERR);
|
|
retval = ERROR_FAIL;
|
|
break;
|
|
}
|
|
|
|
if (buf_get_u32(reg_params[3].value, 0, 32) & FLASH_WRPRTERR)
|
|
{
|
|
LOG_ERROR("flash memory write protected");
|
|
/* Clear but report errors */
|
|
target_write_u32(target, STM32_FLASH_SR, FLASH_WRPRTERR);
|
|
retval = ERROR_FAIL;
|
|
break;
|
|
}
|
|
|
|
buffer += thisrun_count * 2;
|
|
address += thisrun_count * 2;
|
|
count -= thisrun_count;
|
|
}
|
|
|
|
target_free_working_area(target, source);
|
|
target_free_working_area(target, stm32x_info->write_algorithm);
|
|
|
|
destroy_reg_param(®_params[0]);
|
|
destroy_reg_param(®_params[1]);
|
|
destroy_reg_param(®_params[2]);
|
|
destroy_reg_param(®_params[3]);
|
|
|
|
return retval;
|
|
}
|
|
|
|
static int stm32x_write(struct flash_bank *bank, uint8_t *buffer,
|
|
uint32_t offset, uint32_t count)
|
|
{
|
|
struct target *target = bank->target;
|
|
uint32_t words_remaining = (count / 2);
|
|
uint32_t bytes_remaining = (count & 0x00000001);
|
|
uint32_t address = bank->base + offset;
|
|
uint32_t bytes_written = 0;
|
|
int retval;
|
|
|
|
if (bank->target->state != TARGET_HALTED)
|
|
{
|
|
LOG_ERROR("Target not halted");
|
|
return ERROR_TARGET_NOT_HALTED;
|
|
}
|
|
|
|
if (offset & 0x1)
|
|
{
|
|
LOG_WARNING("offset 0x%" PRIx32 " breaks required 2-byte alignment", offset);
|
|
return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
|
|
}
|
|
|
|
/* unlock flash registers */
|
|
retval = target_write_u32(target, STM32_FLASH_KEYR, KEY1);
|
|
if (retval != ERROR_OK)
|
|
return retval;
|
|
retval = target_write_u32(target, STM32_FLASH_KEYR, KEY2);
|
|
if (retval != ERROR_OK)
|
|
return retval;
|
|
|
|
/* multiple half words (2-byte) to be programmed? */
|
|
if (words_remaining > 0)
|
|
{
|
|
/* try using a block write */
|
|
if ((retval = stm32x_write_block(bank, buffer, offset, words_remaining)) != ERROR_OK)
|
|
{
|
|
if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
|
|
{
|
|
/* if block write failed (no sufficient working area),
|
|
* we use normal (slow) single dword accesses */
|
|
LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
|
|
}
|
|
}
|
|
else
|
|
{
|
|
buffer += words_remaining * 2;
|
|
address += words_remaining * 2;
|
|
words_remaining = 0;
|
|
}
|
|
}
|
|
|
|
if ((retval != ERROR_OK) && (retval != ERROR_TARGET_RESOURCE_NOT_AVAILABLE))
|
|
return retval;
|
|
|
|
while (words_remaining > 0)
|
|
{
|
|
uint16_t value;
|
|
memcpy(&value, buffer + bytes_written, sizeof(uint16_t));
|
|
|
|
retval = target_write_u32(target, STM32_FLASH_CR, FLASH_PG);
|
|
if (retval != ERROR_OK)
|
|
return retval;
|
|
retval = target_write_u16(target, address, value);
|
|
if (retval != ERROR_OK)
|
|
return retval;
|
|
|
|
retval = stm32x_wait_status_busy(bank, 5);
|
|
if (retval != ERROR_OK)
|
|
return retval;
|
|
|
|
bytes_written += 2;
|
|
words_remaining--;
|
|
address += 2;
|
|
}
|
|
|
|
if (bytes_remaining)
|
|
{
|
|
uint16_t value = 0xffff;
|
|
memcpy(&value, buffer + bytes_written, bytes_remaining);
|
|
|
|
retval = target_write_u32(target, STM32_FLASH_CR, FLASH_PG);
|
|
if (retval != ERROR_OK)
|
|
return retval;
|
|
retval = target_write_u16(target, address, value);
|
|
if (retval != ERROR_OK)
|
|
return retval;
|
|
|
|
retval = stm32x_wait_status_busy(bank, 5);
|
|
if (retval != ERROR_OK)
|
|
return retval;
|
|
}
|
|
|
|
return target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
|
|
}
|
|
|
|
static int stm32x_probe(struct flash_bank *bank)
|
|
{
|
|
struct target *target = bank->target;
|
|
struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
|
|
int i;
|
|
uint16_t num_pages;
|
|
uint32_t device_id;
|
|
int page_size;
|
|
|
|
stm32x_info->probed = 0;
|
|
|
|
/* read stm32 device id register */
|
|
int retval = target_read_u32(target, 0xE0042000, &device_id);
|
|
if (retval != ERROR_OK)
|
|
return retval;
|
|
LOG_INFO("device id = 0x%08" PRIx32 "", device_id);
|
|
|
|
/* get flash size from target. */
|
|
retval = target_read_u16(target, 0x1FFFF7E0, &num_pages);
|
|
if (retval != ERROR_OK)
|
|
{
|
|
LOG_WARNING("failed reading flash size, default to max target family");
|
|
/* failed reading flash size, default to max target family */
|
|
num_pages = 0xffff;
|
|
}
|
|
|
|
if ((device_id & 0x7ff) == 0x410)
|
|
{
|
|
/* medium density - we have 1k pages
|
|
* 4 pages for a protection area */
|
|
page_size = 1024;
|
|
stm32x_info->ppage_size = 4;
|
|
|
|
/* check for early silicon */
|
|
if (num_pages == 0xffff)
|
|
{
|
|
/* number of sectors incorrect on revA */
|
|
LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 128k flash");
|
|
num_pages = 128;
|
|
}
|
|
}
|
|
else if ((device_id & 0x7ff) == 0x412)
|
|
{
|
|
/* low density - we have 1k pages
|
|
* 4 pages for a protection area */
|
|
page_size = 1024;
|
|
stm32x_info->ppage_size = 4;
|
|
|
|
/* check for early silicon */
|
|
if (num_pages == 0xffff)
|
|
{
|
|
/* number of sectors incorrect on revA */
|
|
LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 32k flash");
|
|
num_pages = 32;
|
|
}
|
|
}
|
|
else if ((device_id & 0x7ff) == 0x414)
|
|
{
|
|
/* high density - we have 2k pages
|
|
* 2 pages for a protection area */
|
|
page_size = 2048;
|
|
stm32x_info->ppage_size = 2;
|
|
|
|
/* check for early silicon */
|
|
if (num_pages == 0xffff)
|
|
{
|
|
/* number of sectors incorrect on revZ */
|
|
LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 512k flash");
|
|
num_pages = 512;
|
|
}
|
|
}
|
|
else if ((device_id & 0x7ff) == 0x418)
|
|
{
|
|
/* connectivity line density - we have 2k pages
|
|
* 2 pages for a protection area */
|
|
page_size = 2048;
|
|
stm32x_info->ppage_size = 2;
|
|
|
|
/* check for early silicon */
|
|
if (num_pages == 0xffff)
|
|
{
|
|
/* number of sectors incorrect on revZ */
|
|
LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 256k flash");
|
|
num_pages = 256;
|
|
}
|
|
}
|
|
else if ((device_id & 0x7ff) == 0x420)
|
|
{
|
|
/* value line density - we have 1k pages
|
|
* 4 pages for a protection area */
|
|
page_size = 1024;
|
|
stm32x_info->ppage_size = 4;
|
|
|
|
/* check for early silicon */
|
|
if (num_pages == 0xffff)
|
|
{
|
|
/* number of sectors may be incorrrect on early silicon */
|
|
LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 128k flash");
|
|
num_pages = 128;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
LOG_WARNING("Cannot identify target as a STM32 family.");
|
|
return ERROR_FAIL;
|
|
}
|
|
|
|
LOG_INFO("flash size = %dkbytes", num_pages);
|
|
|
|
/* calculate numbers of pages */
|
|
num_pages /= (page_size / 1024);
|
|
|
|
if (bank->sectors)
|
|
{
|
|
free(bank->sectors);
|
|
bank->sectors = NULL;
|
|
}
|
|
|
|
bank->base = 0x08000000;
|
|
bank->size = (num_pages * page_size);
|
|
bank->num_sectors = num_pages;
|
|
bank->sectors = malloc(sizeof(struct flash_sector) * num_pages);
|
|
|
|
for (i = 0; i < num_pages; i++)
|
|
{
|
|
bank->sectors[i].offset = i * page_size;
|
|
bank->sectors[i].size = page_size;
|
|
bank->sectors[i].is_erased = -1;
|
|
bank->sectors[i].is_protected = 1;
|
|
}
|
|
|
|
stm32x_info->probed = 1;
|
|
|
|
return ERROR_OK;
|
|
}
|
|
|
|
static int stm32x_auto_probe(struct flash_bank *bank)
|
|
{
|
|
struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
|
|
if (stm32x_info->probed)
|
|
return ERROR_OK;
|
|
return stm32x_probe(bank);
|
|
}
|
|
|
|
#if 0
|
|
COMMAND_HANDLER(stm32x_handle_part_id_command)
|
|
{
|
|
return ERROR_OK;
|
|
}
|
|
#endif
|
|
|
|
static int get_stm32x_info(struct flash_bank *bank, char *buf, int buf_size)
|
|
{
|
|
struct target *target = bank->target;
|
|
uint32_t device_id;
|
|
int printed;
|
|
|
|
/* read stm32 device id register */
|
|
int retval = target_read_u32(target, 0xE0042000, &device_id);
|
|
if (retval != ERROR_OK)
|
|
return retval;
|
|
|
|
if ((device_id & 0x7ff) == 0x410)
|
|
{
|
|
printed = snprintf(buf, buf_size, "stm32x (Medium Density) - Rev: ");
|
|
buf += printed;
|
|
buf_size -= printed;
|
|
|
|
switch (device_id >> 16)
|
|
{
|
|
case 0x0000:
|
|
snprintf(buf, buf_size, "A");
|
|
break;
|
|
|
|
case 0x2000:
|
|
snprintf(buf, buf_size, "B");
|
|
break;
|
|
|
|
case 0x2001:
|
|
snprintf(buf, buf_size, "Z");
|
|
break;
|
|
|
|
case 0x2003:
|
|
snprintf(buf, buf_size, "Y");
|
|
break;
|
|
|
|
default:
|
|
snprintf(buf, buf_size, "unknown");
|
|
break;
|
|
}
|
|
}
|
|
else if ((device_id & 0x7ff) == 0x412)
|
|
{
|
|
printed = snprintf(buf, buf_size, "stm32x (Low Density) - Rev: ");
|
|
buf += printed;
|
|
buf_size -= printed;
|
|
|
|
switch (device_id >> 16)
|
|
{
|
|
case 0x1000:
|
|
snprintf(buf, buf_size, "A");
|
|
break;
|
|
|
|
default:
|
|
snprintf(buf, buf_size, "unknown");
|
|
break;
|
|
}
|
|
}
|
|
else if ((device_id & 0x7ff) == 0x414)
|
|
{
|
|
printed = snprintf(buf, buf_size, "stm32x (High Density) - Rev: ");
|
|
buf += printed;
|
|
buf_size -= printed;
|
|
|
|
switch (device_id >> 16)
|
|
{
|
|
case 0x1000:
|
|
snprintf(buf, buf_size, "A");
|
|
break;
|
|
|
|
case 0x1001:
|
|
snprintf(buf, buf_size, "Z");
|
|
break;
|
|
|
|
default:
|
|
snprintf(buf, buf_size, "unknown");
|
|
break;
|
|
}
|
|
}
|
|
else if ((device_id & 0x7ff) == 0x418)
|
|
{
|
|
printed = snprintf(buf, buf_size, "stm32x (Connectivity) - Rev: ");
|
|
buf += printed;
|
|
buf_size -= printed;
|
|
|
|
switch (device_id >> 16)
|
|
{
|
|
case 0x1000:
|
|
snprintf(buf, buf_size, "A");
|
|
break;
|
|
|
|
case 0x1001:
|
|
snprintf(buf, buf_size, "Z");
|
|
break;
|
|
|
|
default:
|
|
snprintf(buf, buf_size, "unknown");
|
|
break;
|
|
}
|
|
}
|
|
else if ((device_id & 0x7ff) == 0x420)
|
|
{
|
|
printed = snprintf(buf, buf_size, "stm32x (Value) - Rev: ");
|
|
buf += printed;
|
|
buf_size -= printed;
|
|
|
|
switch (device_id >> 16)
|
|
{
|
|
case 0x1000:
|
|
snprintf(buf, buf_size, "A");
|
|
break;
|
|
|
|
case 0x1001:
|
|
snprintf(buf, buf_size, "Z");
|
|
break;
|
|
|
|
default:
|
|
snprintf(buf, buf_size, "unknown");
|
|
break;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
snprintf(buf, buf_size, "Cannot identify target as a stm32x\n");
|
|
return ERROR_FAIL;
|
|
}
|
|
|
|
return ERROR_OK;
|
|
}
|
|
|
|
COMMAND_HANDLER(stm32x_handle_lock_command)
|
|
{
|
|
struct target *target = NULL;
|
|
struct stm32x_flash_bank *stm32x_info = NULL;
|
|
|
|
if (CMD_ARGC < 1)
|
|
{
|
|
command_print(CMD_CTX, "stm32x lock <bank>");
|
|
return ERROR_OK;
|
|
}
|
|
|
|
struct flash_bank *bank;
|
|
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
|
|
if (ERROR_OK != retval)
|
|
return retval;
|
|
|
|
stm32x_info = bank->driver_priv;
|
|
|
|
target = bank->target;
|
|
|
|
if (target->state != TARGET_HALTED)
|
|
{
|
|
LOG_ERROR("Target not halted");
|
|
return ERROR_TARGET_NOT_HALTED;
|
|
}
|
|
|
|
if (stm32x_erase_options(bank) != ERROR_OK)
|
|
{
|
|
command_print(CMD_CTX, "stm32x failed to erase options");
|
|
return ERROR_OK;
|
|
}
|
|
|
|
/* set readout protection */
|
|
stm32x_info->option_bytes.RDP = 0;
|
|
|
|
if (stm32x_write_options(bank) != ERROR_OK)
|
|
{
|
|
command_print(CMD_CTX, "stm32x failed to lock device");
|
|
return ERROR_OK;
|
|
}
|
|
|
|
command_print(CMD_CTX, "stm32x locked");
|
|
|
|
return ERROR_OK;
|
|
}
|
|
|
|
COMMAND_HANDLER(stm32x_handle_unlock_command)
|
|
{
|
|
struct target *target = NULL;
|
|
struct stm32x_flash_bank *stm32x_info = NULL;
|
|
|
|
if (CMD_ARGC < 1)
|
|
{
|
|
command_print(CMD_CTX, "stm32x unlock <bank>");
|
|
return ERROR_OK;
|
|
}
|
|
|
|
struct flash_bank *bank;
|
|
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
|
|
if (ERROR_OK != retval)
|
|
return retval;
|
|
|
|
stm32x_info = bank->driver_priv;
|
|
|
|
target = bank->target;
|
|
|
|
if (target->state != TARGET_HALTED)
|
|
{
|
|
LOG_ERROR("Target not halted");
|
|
return ERROR_TARGET_NOT_HALTED;
|
|
}
|
|
|
|
if (stm32x_erase_options(bank) != ERROR_OK)
|
|
{
|
|
command_print(CMD_CTX, "stm32x failed to unlock device");
|
|
return ERROR_OK;
|
|
}
|
|
|
|
if (stm32x_write_options(bank) != ERROR_OK)
|
|
{
|
|
command_print(CMD_CTX, "stm32x failed to lock device");
|
|
return ERROR_OK;
|
|
}
|
|
|
|
command_print(CMD_CTX, "stm32x unlocked.\n"
|
|
"INFO: a reset or power cycle is required "
|
|
"for the new settings to take effect.");
|
|
|
|
return ERROR_OK;
|
|
}
|
|
|
|
COMMAND_HANDLER(stm32x_handle_options_read_command)
|
|
{
|
|
uint32_t optionbyte;
|
|
struct target *target = NULL;
|
|
struct stm32x_flash_bank *stm32x_info = NULL;
|
|
|
|
if (CMD_ARGC < 1)
|
|
{
|
|
command_print(CMD_CTX, "stm32x options_read <bank>");
|
|
return ERROR_OK;
|
|
}
|
|
|
|
struct flash_bank *bank;
|
|
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
|
|
if (ERROR_OK != retval)
|
|
return retval;
|
|
|
|
stm32x_info = bank->driver_priv;
|
|
|
|
target = bank->target;
|
|
|
|
if (target->state != TARGET_HALTED)
|
|
{
|
|
LOG_ERROR("Target not halted");
|
|
return ERROR_TARGET_NOT_HALTED;
|
|
}
|
|
|
|
retval = target_read_u32(target, STM32_FLASH_OBR, &optionbyte);
|
|
if (retval != ERROR_OK)
|
|
return retval;
|
|
command_print(CMD_CTX, "Option Byte: 0x%" PRIx32 "", optionbyte);
|
|
|
|
if (buf_get_u32((uint8_t*)&optionbyte, OPT_ERROR, 1))
|
|
command_print(CMD_CTX, "Option Byte Complement Error");
|
|
|
|
if (buf_get_u32((uint8_t*)&optionbyte, OPT_READOUT, 1))
|
|
command_print(CMD_CTX, "Readout Protection On");
|
|
else
|
|
command_print(CMD_CTX, "Readout Protection Off");
|
|
|
|
if (buf_get_u32((uint8_t*)&optionbyte, OPT_RDWDGSW, 1))
|
|
command_print(CMD_CTX, "Software Watchdog");
|
|
else
|
|
command_print(CMD_CTX, "Hardware Watchdog");
|
|
|
|
if (buf_get_u32((uint8_t*)&optionbyte, OPT_RDRSTSTOP, 1))
|
|
command_print(CMD_CTX, "Stop: No reset generated");
|
|
else
|
|
command_print(CMD_CTX, "Stop: Reset generated");
|
|
|
|
if (buf_get_u32((uint8_t*)&optionbyte, OPT_RDRSTSTDBY, 1))
|
|
command_print(CMD_CTX, "Standby: No reset generated");
|
|
else
|
|
command_print(CMD_CTX, "Standby: Reset generated");
|
|
|
|
return ERROR_OK;
|
|
}
|
|
|
|
COMMAND_HANDLER(stm32x_handle_options_write_command)
|
|
{
|
|
struct target *target = NULL;
|
|
struct stm32x_flash_bank *stm32x_info = NULL;
|
|
uint16_t optionbyte = 0xF8;
|
|
|
|
if (CMD_ARGC < 4)
|
|
{
|
|
command_print(CMD_CTX, "stm32x options_write <bank> <SWWDG | HWWDG> <RSTSTNDBY | NORSTSTNDBY> <RSTSTOP | NORSTSTOP>");
|
|
return ERROR_OK;
|
|
}
|
|
|
|
struct flash_bank *bank;
|
|
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
|
|
if (ERROR_OK != retval)
|
|
return retval;
|
|
|
|
stm32x_info = bank->driver_priv;
|
|
|
|
target = bank->target;
|
|
|
|
if (target->state != TARGET_HALTED)
|
|
{
|
|
LOG_ERROR("Target not halted");
|
|
return ERROR_TARGET_NOT_HALTED;
|
|
}
|
|
|
|
/* REVISIT: ignores some options which we will display...
|
|
* and doesn't insist on the specified syntax.
|
|
*/
|
|
|
|
/* OPT_RDWDGSW */
|
|
if (strcmp(CMD_ARGV[1], "SWWDG") == 0)
|
|
{
|
|
optionbyte |= (1 << 0);
|
|
}
|
|
else /* REVISIT must be "HWWDG" then ... */
|
|
{
|
|
optionbyte &= ~(1 << 0);
|
|
}
|
|
|
|
/* OPT_RDRSTSTDBY */
|
|
if (strcmp(CMD_ARGV[2], "NORSTSTNDBY") == 0)
|
|
{
|
|
optionbyte |= (1 << 1);
|
|
}
|
|
else /* REVISIT must be "RSTSTNDBY" then ... */
|
|
{
|
|
optionbyte &= ~(1 << 1);
|
|
}
|
|
|
|
/* OPT_RDRSTSTOP */
|
|
if (strcmp(CMD_ARGV[3], "NORSTSTOP") == 0)
|
|
{
|
|
optionbyte |= (1 << 2);
|
|
}
|
|
else /* REVISIT must be "RSTSTOP" then ... */
|
|
{
|
|
optionbyte &= ~(1 << 2);
|
|
}
|
|
|
|
if (stm32x_erase_options(bank) != ERROR_OK)
|
|
{
|
|
command_print(CMD_CTX, "stm32x failed to erase options");
|
|
return ERROR_OK;
|
|
}
|
|
|
|
stm32x_info->option_bytes.user_options = optionbyte;
|
|
|
|
if (stm32x_write_options(bank) != ERROR_OK)
|
|
{
|
|
command_print(CMD_CTX, "stm32x failed to write options");
|
|
return ERROR_OK;
|
|
}
|
|
|
|
command_print(CMD_CTX, "stm32x write options complete.\n"
|
|
"INFO: a reset or power cycle is required "
|
|
"for the new settings to take effect.");
|
|
|
|
return ERROR_OK;
|
|
}
|
|
|
|
static int stm32x_mass_erase(struct flash_bank *bank)
|
|
{
|
|
struct target *target = bank->target;
|
|
|
|
if (target->state != TARGET_HALTED)
|
|
{
|
|
LOG_ERROR("Target not halted");
|
|
return ERROR_TARGET_NOT_HALTED;
|
|
}
|
|
|
|
/* unlock option flash registers */
|
|
int retval = target_write_u32(target, STM32_FLASH_KEYR, KEY1);
|
|
if (retval != ERROR_OK)
|
|
return retval;
|
|
retval = target_write_u32(target, STM32_FLASH_KEYR, KEY2);
|
|
if (retval != ERROR_OK)
|
|
return retval;
|
|
|
|
/* mass erase flash memory */
|
|
retval = target_write_u32(target, STM32_FLASH_CR, FLASH_MER);
|
|
if (retval != ERROR_OK)
|
|
return retval;
|
|
retval = target_write_u32(target, STM32_FLASH_CR, FLASH_MER | FLASH_STRT);
|
|
if (retval != ERROR_OK)
|
|
return retval;
|
|
|
|
retval = stm32x_wait_status_busy(bank, 100);
|
|
if (retval != ERROR_OK)
|
|
return retval;
|
|
|
|
retval = target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
|
|
if (retval != ERROR_OK)
|
|
return retval;
|
|
|
|
return ERROR_OK;
|
|
}
|
|
|
|
COMMAND_HANDLER(stm32x_handle_mass_erase_command)
|
|
{
|
|
int i;
|
|
|
|
if (CMD_ARGC < 1)
|
|
{
|
|
command_print(CMD_CTX, "stm32x mass_erase <bank>");
|
|
return ERROR_OK;
|
|
}
|
|
|
|
struct flash_bank *bank;
|
|
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
|
|
if (ERROR_OK != retval)
|
|
return retval;
|
|
|
|
retval = stm32x_mass_erase(bank);
|
|
if (retval == ERROR_OK)
|
|
{
|
|
/* set all sectors as erased */
|
|
for (i = 0; i < bank->num_sectors; i++)
|
|
{
|
|
bank->sectors[i].is_erased = 1;
|
|
}
|
|
|
|
command_print(CMD_CTX, "stm32x mass erase complete");
|
|
}
|
|
else
|
|
{
|
|
command_print(CMD_CTX, "stm32x mass erase failed");
|
|
}
|
|
|
|
return retval;
|
|
}
|
|
|
|
static const struct command_registration stm32x_exec_command_handlers[] = {
|
|
{
|
|
.name = "lock",
|
|
.handler = stm32x_handle_lock_command,
|
|
.mode = COMMAND_EXEC,
|
|
.usage = "bank_id",
|
|
.help = "Lock entire flash device.",
|
|
},
|
|
{
|
|
.name = "unlock",
|
|
.handler = stm32x_handle_unlock_command,
|
|
.mode = COMMAND_EXEC,
|
|
.usage = "bank_id",
|
|
.help = "Unlock entire protected flash device.",
|
|
},
|
|
{
|
|
.name = "mass_erase",
|
|
.handler = stm32x_handle_mass_erase_command,
|
|
.mode = COMMAND_EXEC,
|
|
.usage = "bank_id",
|
|
.help = "Erase entire flash device.",
|
|
},
|
|
{
|
|
.name = "options_read",
|
|
.handler = stm32x_handle_options_read_command,
|
|
.mode = COMMAND_EXEC,
|
|
.usage = "bank_id",
|
|
.help = "Read and display device option byte.",
|
|
},
|
|
{
|
|
.name = "options_write",
|
|
.handler = stm32x_handle_options_write_command,
|
|
.mode = COMMAND_EXEC,
|
|
.usage = "bank_id ('SWWDG'|'HWWDG') "
|
|
"('RSTSTNDBY'|'NORSTSTNDBY') "
|
|
"('RSTSTOP'|'NORSTSTOP')",
|
|
.help = "Replace bits in device option byte.",
|
|
},
|
|
COMMAND_REGISTRATION_DONE
|
|
};
|
|
|
|
static const struct command_registration stm32x_command_handlers[] = {
|
|
{
|
|
.name = "stm32x",
|
|
.mode = COMMAND_ANY,
|
|
.help = "stm32x flash command group",
|
|
.chain = stm32x_exec_command_handlers,
|
|
},
|
|
COMMAND_REGISTRATION_DONE
|
|
};
|
|
|
|
struct flash_driver stm32x_flash = {
|
|
.name = "stm32x",
|
|
.commands = stm32x_command_handlers,
|
|
.flash_bank_command = stm32x_flash_bank_command,
|
|
.erase = stm32x_erase,
|
|
.protect = stm32x_protect,
|
|
.write = stm32x_write,
|
|
.read = default_flash_read,
|
|
.probe = stm32x_probe,
|
|
.auto_probe = stm32x_auto_probe,
|
|
.erase_check = default_flash_mem_blank_check,
|
|
.protect_check = stm32x_protect_check,
|
|
.info = get_stm32x_info,
|
|
};
|