openocd/src/target/riscv
Erhan Kurubas 06c3240155 semihosting: move semihosting_result_t from riscv.h to the semihosting_common.h
These enum values are useful for the arch level semihosting call handlers.
Currently riscv uses them, we also need similar return codes for the xtensa.

Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: I8f63749cc203c59b07862f33edf3c393cd7e33a9
Reviewed-on: https://review.openocd.org/c/openocd/+/7039
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-07-02 08:27:12 +00:00
..
asm.h Upstream tons of RISC-V changes. 2020-10-14 05:43:05 +01:00
batch.c Upstream a whole host of RISC-V changes. 2021-10-25 16:12:05 +00:00
batch.h Upstream tons of RISC-V changes. 2020-10-14 05:43:05 +01:00
debug_defines.h riscv: Regenerated debug_defines.h and encoding.h 2021-11-20 14:39:13 +00:00
encoding.h riscv: Regenerated debug_defines.h and encoding.h 2021-11-20 14:39:13 +00:00
gdb_regs.h Upstream tons of RISC-V changes. 2020-10-14 05:43:05 +01:00
Makefile.am Add RISC-V support. 2018-07-24 13:07:26 +01:00
opcodes.h Upstream a whole host of RISC-V changes. 2021-10-25 16:12:05 +00:00
program.c Upstream tons of RISC-V changes. 2020-10-14 05:43:05 +01:00
program.h Upstream a whole host of RISC-V changes. 2021-10-25 16:12:05 +00:00
riscv_semihosting.c semihosting: move semihosting_result_t from riscv.h to the semihosting_common.h 2022-07-02 08:27:12 +00:00
riscv-011.c Upstream a whole host of RISC-V changes. 2021-10-25 16:12:05 +00:00
riscv-013.c target/riscv: fix 'reset run' after 'reset halt' 2022-05-18 09:03:41 +00:00
riscv.c semihosting: move semihosting_result_t from riscv.h to the semihosting_common.h 2022-07-02 08:27:12 +00:00
riscv.h semihosting: move semihosting_result_t from riscv.h to the semihosting_common.h 2022-07-02 08:27:12 +00:00