235 lines
7.4 KiB
C
235 lines
7.4 KiB
C
/***************************************************************************
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* Copyright (C) 2007 by Dominic Rath <Dominic.Rath@gmx.de> *
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* Copyright (C) 2009 Zachary T Welch <zw@superlucidity.net> *
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* *
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* Partially based on linux/include/linux/mtd/nand.h *
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* Copyright (C) 2000 David Woodhouse <dwmw2@mvhi.com> *
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* Copyright (C) 2000 Steven J. Hill <sjhill@realitydiluted.com> *
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* Copyright (C) 2000 Thomas Gleixner <tglx@linutronix.de> *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, write to the *
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* Free Software Foundation, Inc., *
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
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***************************************************************************/
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#ifndef FLASH_NAND_CORE_H
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#define FLASH_NAND_CORE_H
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#include <flash/common.h>
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/**
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* Representation of a single NAND block in a NAND device.
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*/
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struct nand_block {
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/** Offset to the block. */
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uint32_t offset;
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/** Size of the block. */
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uint32_t size;
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/** True if the block has been erased. */
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int is_erased;
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/** True if the block is bad. */
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int is_bad;
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};
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struct nand_oobfree {
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int offset;
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int length;
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};
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struct nand_ecclayout {
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int eccbytes;
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int eccpos[64];
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int oobavail;
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struct nand_oobfree oobfree[2];
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};
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struct nand_device {
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const char *name;
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struct target *target;
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struct nand_flash_controller *controller;
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void *controller_priv;
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struct nand_manufacturer *manufacturer;
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struct nand_info *device;
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int bus_width;
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int address_cycles;
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int page_size;
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int erase_size;
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int use_raw;
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int num_blocks;
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struct nand_block *blocks;
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struct nand_device *next;
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};
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/* NAND Flash Manufacturer ID Codes
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*/
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enum {
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NAND_MFR_TOSHIBA = 0x98,
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NAND_MFR_SAMSUNG = 0xec,
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NAND_MFR_FUJITSU = 0x04,
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NAND_MFR_NATIONAL = 0x8f,
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NAND_MFR_RENESAS = 0x07,
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NAND_MFR_STMICRO = 0x20,
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NAND_MFR_HYNIX = 0xad,
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NAND_MFR_MICRON = 0x2c,
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};
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struct nand_manufacturer {
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int id;
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const char *name;
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};
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struct nand_info {
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int mfr_id;
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int id;
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int page_size;
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int chip_size;
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int erase_size;
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int options;
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const char *name;
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};
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/* Option constants for bizarre disfunctionality and real features
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*/
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enum {
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/* Chip can not auto increment pages */
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NAND_NO_AUTOINCR = 0x00000001,
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/* Buswitdh is 16 bit */
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NAND_BUSWIDTH_16 = 0x00000002,
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/* Device supports partial programming without padding */
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NAND_NO_PADDING = 0x00000004,
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/* Chip has cache program function */
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NAND_CACHEPRG = 0x00000008,
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/* Chip has copy back function */
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NAND_COPYBACK = 0x00000010,
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/* AND Chip which has 4 banks and a confusing page / block
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* assignment. See Renesas datasheet for further information */
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NAND_IS_AND = 0x00000020,
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/* Chip has a array of 4 pages which can be read without
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* additional ready /busy waits */
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NAND_4PAGE_ARRAY = 0x00000040,
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/* Chip requires that BBT is periodically rewritten to prevent
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* bits from adjacent blocks from 'leaking' in altering data.
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* This happens with the Renesas AG-AND chips, possibly others. */
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BBT_AUTO_REFRESH = 0x00000080,
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/* Chip does not require ready check on read. True
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* for all large page devices, as they do not support
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* autoincrement.*/
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NAND_NO_READRDY = 0x00000100,
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/* Options valid for Samsung large page devices */
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NAND_SAMSUNG_LP_OPTIONS = (NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK),
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/* Options for new chips with large page size. The pagesize and the
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* erasesize is determined from the extended id bytes
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*/
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LP_OPTIONS = (NAND_SAMSUNG_LP_OPTIONS | NAND_NO_READRDY | NAND_NO_AUTOINCR),
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LP_OPTIONS16 = (LP_OPTIONS | NAND_BUSWIDTH_16),
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};
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enum {
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/* Standard NAND flash commands */
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NAND_CMD_READ0 = 0x0,
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NAND_CMD_READ1 = 0x1,
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NAND_CMD_RNDOUT = 0x5,
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NAND_CMD_PAGEPROG = 0x10,
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NAND_CMD_READOOB = 0x50,
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NAND_CMD_ERASE1 = 0x60,
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NAND_CMD_STATUS = 0x70,
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NAND_CMD_STATUS_MULTI = 0x71,
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NAND_CMD_SEQIN = 0x80,
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NAND_CMD_RNDIN = 0x85,
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NAND_CMD_READID = 0x90,
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NAND_CMD_ERASE2 = 0xd0,
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NAND_CMD_RESET = 0xff,
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/* Extended commands for large page devices */
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NAND_CMD_READSTART = 0x30,
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NAND_CMD_RNDOUTSTART = 0xE0,
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NAND_CMD_CACHEDPROG = 0x15,
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};
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/* Status bits */
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enum {
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NAND_STATUS_FAIL = 0x01,
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NAND_STATUS_FAIL_N1 = 0x02,
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NAND_STATUS_TRUE_READY = 0x20,
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NAND_STATUS_READY = 0x40,
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NAND_STATUS_WP = 0x80,
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};
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/* OOB (spare) data formats */
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enum oob_formats {
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NAND_OOB_NONE = 0x0, /* no OOB data at all */
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NAND_OOB_RAW = 0x1, /* raw OOB data (16 bytes for 512b page sizes, 64 bytes for
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*2048b page sizes) */
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NAND_OOB_ONLY = 0x2, /* only OOB data */
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NAND_OOB_SW_ECC = 0x10, /* when writing, use SW ECC (as opposed to no ECC) */
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NAND_OOB_HW_ECC = 0x20, /* when writing, use HW ECC (as opposed to no ECC) */
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NAND_OOB_SW_ECC_KW = 0x40, /* when writing, use Marvell's Kirkwood bootrom format */
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NAND_OOB_JFFS2 = 0x100, /* when writing, use JFFS2 OOB layout */
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NAND_OOB_YAFFS2 = 0x100,/* when writing, use YAFFS2 OOB layout */
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};
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struct nand_device *get_nand_device_by_num(int num);
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int nand_page_command(struct nand_device *nand, uint32_t page,
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uint8_t cmd, bool oob_only);
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int nand_read_data_page(struct nand_device *nand, uint8_t *data, uint32_t size);
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int nand_write_data_page(struct nand_device *nand,
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uint8_t *data, uint32_t size);
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int nand_write_finish(struct nand_device *nand);
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int nand_read_page_raw(struct nand_device *nand, uint32_t page,
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uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size);
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int nand_write_page_raw(struct nand_device *nand, uint32_t page,
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uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size);
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int nand_read_status(struct nand_device *nand, uint8_t *status);
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int nand_calculate_ecc(struct nand_device *nand,
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const uint8_t *dat, uint8_t *ecc_code);
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int nand_calculate_ecc_kw(struct nand_device *nand,
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const uint8_t *dat, uint8_t *ecc_code);
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int nand_register_commands(struct command_context *cmd_ctx);
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/** helper for parsing a nand device command argument string */
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COMMAND_HELPER(nand_command_get_device, unsigned name_index,
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struct nand_device **nand);
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#define ERROR_NAND_DEVICE_INVALID (-1100)
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#define ERROR_NAND_OPERATION_FAILED (-1101)
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#define ERROR_NAND_OPERATION_TIMEOUT (-1102)
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#define ERROR_NAND_OPERATION_NOT_SUPPORTED (-1103)
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#define ERROR_NAND_DEVICE_NOT_PROBED (-1104)
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#define ERROR_NAND_ERROR_CORRECTION_FAILED (-1105)
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#define ERROR_NAND_NO_BUFFER (-1106)
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#endif /* FLASH_NAND_CORE_H */
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