168 lines
7.1 KiB
C
168 lines
7.1 KiB
C
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/***************************************************************************
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* Copyright (C) 2009 by Alexei Babich *
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* Rezonans plc., Chelyabinsk, Russia *
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* impatt@mail.ru *
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* *
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* Copyright (C) 2011 by Erik Ahlen *
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* Avalon Innovation, Sweden *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, write to the *
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* Free Software Foundation, Inc., *
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
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***************************************************************************/
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/*
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* Freescale iMX OpenOCD NAND Flash controller support.
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* based on Freescale iMX2* and iMX3* OpenOCD NAND Flash controller support.
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*
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* Many thanks to Ben Dooks for writing s3c24xx driver.
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*/
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#define MXC_NF_BUFSIZ (mxc_nf_info->mxc_regs_addr + 0x00)
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#define MXC_NF_BUFADDR (mxc_nf_info->mxc_regs_addr + 0x04)
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#define MXC_NF_FADDR (mxc_nf_info->mxc_regs_addr + 0x06)
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#define MXC_NF_FCMD (mxc_nf_info->mxc_regs_addr + 0x08)
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#define MXC_NF_BUFCFG (mxc_nf_info->mxc_regs_addr + 0x0a)
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#define MXC_NF_ECCSTATUS (mxc_nf_info->mxc_regs_addr + 0x0c)
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#define MXC_NF_ECCMAINPOS (mxc_nf_info->mxc_regs_addr + 0x0e)
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#define MXC_NF_V1_ECCSPAREPOS (mxc_nf_info->mxc_regs_addr + 0x10)
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#define MXC_NF_V2_SPAS (mxc_nf_info->mxc_regs_addr + 0x10)
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#define MXC_NF_FWP (mxc_nf_info->mxc_regs_addr + 0x12)
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#define MXC_NF_V1_UNLOCKSTART (mxc_nf_info->mxc_regs_addr + 0x14)
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#define MXC_NF_V1_UNLOCKEND (mxc_nf_info->mxc_regs_addr + 0x16)
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#define MXC_NF_V2_UNLOCKSTART0 (mxc_nf_info->mxc_regs_addr + 0x20)
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#define MXC_NF_V2_UNLOCKSTART1 (mxc_nf_info->mxc_regs_addr + 0x24)
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#define MXC_NF_V2_UNLOCKSTART2 (mxc_nf_info->mxc_regs_addr + 0x28)
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#define MXC_NF_V2_UNLOCKSTART3 (mxc_nf_info->mxc_regs_addr + 0x2c)
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#define MXC_NF_V2_UNLOCKEND0 (mxc_nf_info->mxc_regs_addr + 0x22)
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#define MXC_NF_V2_UNLOCKEND1 (mxc_nf_info->mxc_regs_addr + 0x26)
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#define MXC_NF_V2_UNLOCKEND2 (mxc_nf_info->mxc_regs_addr + 0x2a)
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#define MXC_NF_V2_UNLOCKEND3 (mxc_nf_info->mxc_regs_addr + 0x2e)
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#define MXC_NF_FWPSTATUS (mxc_nf_info->mxc_regs_addr + 0x18)
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/*
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* all bits not marked as self-clearing bit
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*/
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#define MXC_NF_CFG1 (mxc_nf_info->mxc_regs_addr + 0x1a)
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#define MXC_NF_CFG2 (mxc_nf_info->mxc_regs_addr + 0x1c)
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#define MXC_NF_MAIN_BUFFER0 (mxc_nf_info->mxc_base_addr + 0x0000)
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#define MXC_NF_MAIN_BUFFER1 (mxc_nf_info->mxc_base_addr + 0x0200)
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#define MXC_NF_MAIN_BUFFER2 (mxc_nf_info->mxc_base_addr + 0x0400)
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#define MXC_NF_MAIN_BUFFER3 (mxc_nf_info->mxc_base_addr + 0x0600)
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#define MXC_NF_V1_SPARE_BUFFER0 (mxc_nf_info->mxc_base_addr + 0x0800)
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#define MXC_NF_V1_SPARE_BUFFER1 (mxc_nf_info->mxc_base_addr + 0x0810)
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#define MXC_NF_V1_SPARE_BUFFER2 (mxc_nf_info->mxc_base_addr + 0x0820)
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#define MXC_NF_V1_SPARE_BUFFER3 (mxc_nf_info->mxc_base_addr + 0x0830)
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#define MXC_NF_V2_MAIN_BUFFER4 (mxc_nf_info->mxc_base_addr + 0x0800)
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#define MXC_NF_V2_MAIN_BUFFER5 (mxc_nf_info->mxc_base_addr + 0x0a00)
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#define MXC_NF_V2_MAIN_BUFFER6 (mxc_nf_info->mxc_base_addr + 0x0c00)
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#define MXC_NF_V2_MAIN_BUFFER7 (mxc_nf_info->mxc_base_addr + 0x0e00)
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#define MXC_NF_V2_SPARE_BUFFER0 (mxc_nf_info->mxc_base_addr + 0x1000)
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#define MXC_NF_V2_SPARE_BUFFER1 (mxc_nf_info->mxc_base_addr + 0x1040)
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#define MXC_NF_V2_SPARE_BUFFER2 (mxc_nf_info->mxc_base_addr + 0x1080)
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#define MXC_NF_V2_SPARE_BUFFER3 (mxc_nf_info->mxc_base_addr + 0x10c0)
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#define MXC_NF_V2_SPARE_BUFFER4 (mxc_nf_info->mxc_base_addr + 0x1100)
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#define MXC_NF_V2_SPARE_BUFFER5 (mxc_nf_info->mxc_base_addr + 0x1140)
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#define MXC_NF_V2_SPARE_BUFFER6 (mxc_nf_info->mxc_base_addr + 0x1180)
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#define MXC_NF_V2_SPARE_BUFFER7 (mxc_nf_info->mxc_base_addr + 0x11c0)
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#define MXC_NF_MAIN_BUFFER_LEN 512
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#define MXC_NF_SPARE_BUFFER_LEN 16
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#define MXC_NF_SPARE_BUFFER_MAX 64
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#define MXC_NF_V1_LAST_BUFFADDR ((MXC_NF_V1_SPARE_BUFFER3) + \
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MXC_NF_SPARE_BUFFER_LEN - 2)
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#define MXC_NF_V2_LAST_BUFFADDR ((MXC_NF_V2_SPARE_BUFFER7) + \
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MXC_NF_SPARE_BUFFER_LEN - 2)
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/* bits in MXC_NF_CFG1 register */
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#define MXC_NF_BIT_ECC_4BIT (1<<0)
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#define MXC_NF_BIT_SPARE_ONLY_EN (1<<2)
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#define MXC_NF_BIT_ECC_EN (1<<3)
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#define MXC_NF_BIT_INT_DIS (1<<4)
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#define MXC_NF_BIT_BE_EN (1<<5)
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#define MXC_NF_BIT_RESET_EN (1<<6)
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#define MXC_NF_BIT_FORCE_CE (1<<7)
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#define MXC_NF_V2_CFG1_PPB(x) (((x) & 0x3) << 9)
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/* bits in MXC_NF_CFG2 register */
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/*Flash Command Input*/
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#define MXC_NF_BIT_OP_FCI (1<<0)
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/*
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* Flash Address Input
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*/
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#define MXC_NF_BIT_OP_FAI (1<<1)
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/*
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* Flash Data Input
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*/
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#define MXC_NF_BIT_OP_FDI (1<<2)
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/* see "enum mx_dataout_type" below */
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#define MXC_NF_BIT_DATAOUT_TYPE(x) ((x)<<3)
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#define MXC_NF_BIT_OP_DONE (1<<15)
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#define MXC_CCM_CGR2 0x53f80028
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#define MXC_GPR 0x43fac008
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#define MX2_FMCR 0x10027814
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#define MX2_FMCR_NF_16BIT_SEL (1<<4)
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#define MX2_FMCR_NF_FMS (1<<5)
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#define MX25_RCSR 0x53f80018
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#define MX25_RCSR_NF_16BIT_SEL (1<<14)
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#define MX25_RCSR_NF_FMS (1<<8)
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#define MX25_RCSR_NF_4K (1<<9)
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#define MX3_PCSR 0x53f8000c
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#define MX3_PCSR_NF_16BIT_SEL (1<<31)
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#define MX3_PCSR_NF_FMS (1<<30)
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#define MX35_RCSR 0x53f80018
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#define MX35_RCSR_NF_16BIT_SEL (1<<14)
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#define MX35_RCSR_NF_FMS (1<<8)
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#define MX35_RCSR_NF_4K (1<<9)
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enum mxc_version {
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MXC_VERSION_UKWN = 0,
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MXC_VERSION_MX25 = 1,
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MXC_VERSION_MX27 = 2,
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MXC_VERSION_MX31 = 3,
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MXC_VERSION_MX35 = 4
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};
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enum mxc_dataout_type {
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MXC_NF_DATAOUT_PAGE = 1,
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MXC_NF_DATAOUT_NANDID = 2,
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MXC_NF_DATAOUT_NANDSTATUS = 4,
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};
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enum mxc_nf_finalize_action {
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MXC_NF_FIN_NONE,
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MXC_NF_FIN_DATAOUT,
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};
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struct mxc_nf_flags {
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unsigned host_little_endian:1;
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unsigned target_little_endian:1;
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unsigned nand_readonly:1;
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unsigned one_kb_sram:1;
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unsigned hw_ecc_enabled:1;
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unsigned biswap_enabled:1;
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};
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struct mxc_nf_controller {
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enum mxc_version mxc_version;
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uint32_t mxc_base_addr;
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uint32_t mxc_regs_addr;
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enum mxc_dataout_type optype;
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enum mxc_nf_finalize_action fin;
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struct mxc_nf_flags flags;
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};
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