666 lines
22 KiB
C
666 lines
22 KiB
C
/***************************************************************************
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* Copyright (C) 2006 by Magnus Lundin *
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* lundin@mlu.mine.nu *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, write to the *
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* Free Software Foundation, Inc., *
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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***************************************************************************/
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/***************************************************************************
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* *
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* CoreSight (Light?) SerialWireJtagDebugPort *
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* *
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* CoreSight™ DAP-Lite TRM, ARM DDI 0316A *
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* Cortex-M3™ TRM, ARM DDI 0337C *
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* *
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***************************************************************************/
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#include "replacements.h"
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#include "cortex_m3.h"
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#include "cortex_swjdp.h"
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#include "jtag.h"
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#include "log.h"
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#include <stdlib.h>
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/*
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Transaction Mode:
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swjdp->trans_mode = TRANS_MODE_COMPOSITE;
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Uses Overrun checking mode and does not do actual JTAG send/receive or transaction
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result checking until swjdp_end_transaction()
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This must be done before using or deallocating any return variables.
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swjdp->trans_mode == TRANS_MODE_ATOMIC
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All reads and writes to the AHB bus are checked for valid completion, and return values
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are immediatley available.
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*/
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/***************************************************************************
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* *
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* DPACC and APACC scanchain access through JTAG-DR *
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* *
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***************************************************************************/
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int swjdp_jtag_error_handler(u8 *in_value, void *priv)
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{
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char *caller = priv;
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DEBUG("caller: %s", caller);
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return ERROR_OK;
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}
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/* Scan out and in from target ordered u8 buffers */
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int swjdp_scan(arm_jtag_t *jtag_info, u8 chain, u8 reg_addr, u8 RnW, u8 *outvalue, u8 *invalue, u8 *ack)
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{
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scan_field_t fields[2];
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u8 out_addr_buf;
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error_handler_t error_handler;
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jtag_add_end_state(TAP_RTI);
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error_handler.error_handler = swjdp_jtag_error_handler;
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error_handler.error_handler_priv = "swjdp_scan";
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arm_jtag_set_instr(jtag_info, chain, &error_handler);
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fields[0].device = jtag_info->chain_pos;
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fields[0].num_bits = 3;
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buf_set_u32(&out_addr_buf, 0, 3, ((reg_addr>>1)&0x6) | (RnW&0x1));
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fields[0].out_value = &out_addr_buf;
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fields[0].out_mask = NULL;
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fields[0].in_value = ack;
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fields[0].in_check_value = NULL;
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fields[0].in_check_mask = NULL;
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fields[0].in_handler = NULL;
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fields[0].in_handler_priv = NULL;
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fields[1].device = jtag_info->chain_pos;
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fields[1].num_bits = 32;
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fields[1].out_value = outvalue;
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fields[1].out_mask = NULL;
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fields[1].in_value = invalue;
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fields[1].in_handler = NULL;
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fields[1].in_handler_priv = NULL;
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fields[1].in_check_value = NULL;
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fields[1].in_check_mask = NULL;
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jtag_add_dr_scan(2, fields, -1, NULL);
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return ERROR_OK;
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}
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/* Scan out and in from host ordered u32 variables */
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int swjdp_scan_u32(arm_jtag_t *jtag_info, u8 chain, u8 reg_addr, u8 RnW, u32 outvalue, u32 *invalue, u8 *ack)
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{
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scan_field_t fields[2];
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u8 out_value_buf[4];
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u8 out_addr_buf;
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error_handler_t error_handler;
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jtag_add_end_state(TAP_RTI);
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error_handler.error_handler = swjdp_jtag_error_handler;
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error_handler.error_handler_priv = "swjdp_scan_u32";
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arm_jtag_set_instr(jtag_info, chain, &error_handler);
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fields[0].device = jtag_info->chain_pos;
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fields[0].num_bits = 3;
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buf_set_u32(&out_addr_buf, 0, 3, ((reg_addr>>1)&0x6) | (RnW&0x1));
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fields[0].out_value = &out_addr_buf;
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fields[0].out_mask = NULL;
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fields[0].in_value = ack;
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fields[0].in_check_value = NULL;
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fields[0].in_check_mask = NULL;
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fields[0].in_handler = NULL;
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fields[0].in_handler_priv = NULL;
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fields[1].device = jtag_info->chain_pos;
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fields[1].num_bits = 32;
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buf_set_u32(out_value_buf, 0, 32, outvalue);
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fields[1].out_value = out_value_buf;
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fields[1].out_mask = NULL;
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fields[1].in_value = NULL;
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if (invalue)
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{
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fields[1].in_handler = arm_jtag_buf_to_u32;
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fields[1].in_handler_priv = invalue;
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}
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else
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{
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fields[1].in_handler = NULL;
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fields[1].in_handler_priv = NULL;
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}
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fields[1].in_check_value = NULL;
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fields[1].in_check_mask = NULL;
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jtag_add_dr_scan(2, fields, -1, NULL);
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return ERROR_OK;
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}
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/* scan_inout_check adds one extra inscan for DPAP_READ commands to read variables */
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int scan_inout_check(swjdp_common_t *swjdp, u8 chain, u8 reg_addr, u8 RnW, u8 *outvalue, u8 *invalue)
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{
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swjdp_scan(swjdp->jtag_info, chain, reg_addr, RnW, outvalue, NULL, NULL);
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if ((RnW==DPAP_READ) && (invalue != NULL))
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{
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swjdp_scan(swjdp->jtag_info, SWJDP_IR_DPACC, 0xC, DPAP_READ, 0, invalue, &swjdp->ack);
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}
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/* In TRANS_MODE_ATOMIC all SWJDP_IR_APACC transactions wait for ack=OK/FAULT and the check CTRL_STAT */
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if ((chain == SWJDP_IR_APACC)&&(swjdp->trans_mode == TRANS_MODE_ATOMIC))
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{
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return swjdp_transaction_endcheck(swjdp);
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}
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return ERROR_OK;
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}
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int scan_inout_check_u32(swjdp_common_t *swjdp, u8 chain, u8 reg_addr, u8 RnW, u32 outvalue, u32 *invalue)
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{
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swjdp_scan_u32(swjdp->jtag_info, chain, reg_addr, RnW, outvalue, NULL, NULL);
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if ((RnW==DPAP_READ) && (invalue != NULL))
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{
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swjdp_scan_u32(swjdp->jtag_info, SWJDP_IR_DPACC, 0xC, DPAP_READ, 0, invalue, &swjdp->ack);
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}
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/* In TRANS_MODE_ATOMIC all SWJDP_IR_APACC transactions wait for ack=OK/FAULT and the check CTRL_STAT */
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if ((chain == SWJDP_IR_APACC)&&(swjdp->trans_mode == TRANS_MODE_ATOMIC))
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{
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return swjdp_transaction_endcheck(swjdp);
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}
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return ERROR_OK;
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}
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int swjdp_transaction_endcheck(swjdp_common_t *swjdp)
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{
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int waitcount = 0;
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u32 ctrlstat;
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u8 ack=0;
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scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
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jtag_execute_queue();
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swjdp->ack = swjdp->ack&0x7;
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while (swjdp->ack != 2)
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{
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if (swjdp->ack==1)
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{
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waitcount++;
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if (waitcount>100)
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{
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WARNING("Timeout waiting for ACK = OK/FAULT in SWJDP transaction");
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return ERROR_JTAG_DEVICE_ERROR;
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}
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}
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else
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{
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WARNING("Invalid ACK in SWJDP transaction");
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return ERROR_JTAG_DEVICE_ERROR;
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}
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scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
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jtag_execute_queue();
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swjdp->ack = swjdp->ack&0x7;
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}
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/* Check for STICKYERR and STICKYORUN */
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if (ctrlstat & (SSTICKYORUN|SSTICKYERR))
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{
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DEBUG(" swjdp: CTRL/STAT error 0x%x",ctrlstat);
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/* Check power to debug regions */
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if ((ctrlstat&0xf0000000)!=0xf0000000)
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{
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ahbap_debugport_init(swjdp);
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}
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else
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{
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u32 dcb_dhcsr,nvic_shcsr, nvic_bfar, nvic_cfsr;
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if (ctrlstat&SSTICKYORUN) ERROR("SWJ-DP OVERRUN - check clock or reduce jtag speed");
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if (ctrlstat&SSTICKYERR) ERROR("SWJ-DP STICKY ERROR");
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/* Clear Sticky Error Bits */
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scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_WRITE, swjdp->dp_ctrl_stat|SSTICKYORUN|SSTICKYERR, NULL);
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scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
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jtag_execute_queue();
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/* Can we find out the reason for the error ?? */
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ahbap_read_system_atomic_u32(swjdp, DCB_DHCSR, &dcb_dhcsr);
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ahbap_read_system_atomic_u32(swjdp, NVIC_SHCSR, &nvic_shcsr);
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ahbap_read_system_atomic_u32(swjdp, NVIC_CFSR, &nvic_cfsr);
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ahbap_read_system_atomic_u32(swjdp, NVIC_BFAR, &nvic_bfar);
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//DEBUG("dcb_dhcsr %x, nvic_shcsr %x, nvic_cfsr %x, nvic_bfar %x",dcb_dhcsr,nvic_shcsr,nvic_cfsr,nvic_bfar);
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ERROR("dcb_dhcsr %x, nvic_shcsr %x, nvic_cfsr %x, nvic_bfar %x",dcb_dhcsr,nvic_shcsr,nvic_cfsr,nvic_bfar);
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}
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jtag_execute_queue();
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return ERROR_JTAG_DEVICE_ERROR;
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}
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return ERROR_OK;
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}
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/***************************************************************************
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* *
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* DP and AHB-AP register access through APACC and DPACC *
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* *
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***************************************************************************/
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int swjdp_write_dpacc(swjdp_common_t *swjdp, u32 value, u8 reg_addr)
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{
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u8 out_value_buf[4];
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buf_set_u32(out_value_buf, 0, 32, value);
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return scan_inout_check(swjdp, SWJDP_IR_DPACC, reg_addr, DPAP_WRITE, out_value_buf, NULL);
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}
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int swjdp_read_dpacc(swjdp_common_t *swjdp, u32 *value, u8 reg_addr)
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{
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scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, reg_addr, DPAP_READ, 0, value);
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return ERROR_OK;
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}
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int swjdp_bankselect_apacc(swjdp_common_t *swjdp,u32 reg_addr)
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{
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u32 select;
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select = (reg_addr&0xFF0000F0);
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if ( select != swjdp->dp_select_value )
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{
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swjdp_write_dpacc(swjdp, select, DP_SELECT);
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swjdp->dp_select_value = select;
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}
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return ERROR_OK;
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}
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int ahbap_write_reg(swjdp_common_t *swjdp, u32 reg_addr, u8* out_value_buf)
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{
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swjdp_bankselect_apacc(swjdp, reg_addr);
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scan_inout_check(swjdp, SWJDP_IR_APACC, reg_addr, DPAP_WRITE, out_value_buf, NULL);
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return ERROR_OK;
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}
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int ahbap_read_reg(swjdp_common_t *swjdp, u32 reg_addr, u8 *in_value_buf)
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{
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swjdp_bankselect_apacc(swjdp, reg_addr);
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scan_inout_check(swjdp, SWJDP_IR_APACC, reg_addr, DPAP_READ, 0, in_value_buf);
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return ERROR_OK;
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}
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int ahbap_write_reg_u32(swjdp_common_t *swjdp, u32 reg_addr, u32 value)
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{
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u8 out_value_buf[4];
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buf_set_u32(out_value_buf, 0, 32, value);
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swjdp_bankselect_apacc(swjdp, reg_addr);
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scan_inout_check(swjdp, SWJDP_IR_APACC, reg_addr, DPAP_WRITE, out_value_buf, NULL);
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return ERROR_OK;
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}
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int ahbap_read_reg_u32(swjdp_common_t *swjdp, u32 reg_addr, u32 *value)
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{
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swjdp_bankselect_apacc(swjdp, reg_addr);
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scan_inout_check_u32(swjdp, SWJDP_IR_APACC, reg_addr, DPAP_READ, 0, value);
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return ERROR_OK;
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}
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/***************************************************************************
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* *
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* AHB-AP access to memory and system registers on AHB bus *
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* *
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***************************************************************************/
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int ahbap_setup_accessport(swjdp_common_t *swjdp, u32 csw, u32 tar)
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{
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csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT;
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if ( csw != swjdp->ap_csw_value )
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{
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//DEBUG("swjdp : Set CSW %x",csw);
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ahbap_write_reg_u32(swjdp, AHBAP_CSW, csw );
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swjdp->ap_csw_value = csw;
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}
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if ( tar != swjdp->ap_tar_value )
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{
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//DEBUG("swjdp : Set TAR %x",tar);
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ahbap_write_reg_u32(swjdp, AHBAP_TAR, tar );
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swjdp->ap_tar_value = tar;
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}
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if (csw & CSW_ADDRINC_MASK)
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{
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/* Do not cache TAR value when autoincrementing */
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swjdp->ap_tar_value = -1;
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}
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return ERROR_OK;
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}
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/*****************************************************************************
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* *
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* ahbap_read_system_u32(swjdp_common_t *swjdp, u32 address, u32 *value) *
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* *
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* Read a u32 value from memory or system register *
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* Functionally equivalent to target_read_u32(target, address, u32 *value), *
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* but with less overhead *
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*****************************************************************************/
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int ahbap_read_system_u32(swjdp_common_t *swjdp, u32 address, u32 *value)
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{
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swjdp->trans_mode = TRANS_MODE_COMPOSITE;
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ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, address&0xFFFFFFF0);
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ahbap_read_reg_u32(swjdp, AHBAP_BD0|address&0xC, value );
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return ERROR_OK;
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}
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int ahbap_read_system_atomic_u32(swjdp_common_t *swjdp, u32 address, u32 *value)
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{
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ahbap_read_system_u32(swjdp, address, value);
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return swjdp_transaction_endcheck(swjdp);
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}
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/*****************************************************************************
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* *
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* ahbap_write_system_u32(swjdp_common_t *swjdp, u32 address, u32 value) *
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* *
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* Write a u32 value to memory or system register *
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* *
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*****************************************************************************/
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int ahbap_write_system_u32(swjdp_common_t *swjdp, u32 address, u32 value)
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{
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swjdp->trans_mode = TRANS_MODE_COMPOSITE;
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ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, address&0xFFFFFFF0);
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ahbap_write_reg_u32(swjdp, AHBAP_BD0|address&0xC, value );
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return ERROR_OK;
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}
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int ahbap_write_system_atomic_u32(swjdp_common_t *swjdp, u32 address, u32 value)
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{
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ahbap_write_system_u32(swjdp, address, value);
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return swjdp_transaction_endcheck(swjdp);
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}
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/*****************************************************************************
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* *
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* ahbap_write_buf(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address) *
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* *
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* Write a buffer in target order (little endian) *
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* *
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*****************************************************************************/
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int ahbap_write_buf(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
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{
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u32 outvalue;
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int wcount, blocksize, writecount, errorcount=0, retval=ERROR_OK;
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swjdp->trans_mode = TRANS_MODE_COMPOSITE;
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while ( (address&0x3)&&(count>0) )
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{
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ahbap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
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outvalue = (*buffer++)<<8*(address&0x3) ;
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ahbap_write_reg_u32(swjdp, AHBAP_DRW, outvalue );
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swjdp_transaction_endcheck(swjdp);
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count--;
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address++;
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}
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wcount = count>>2;
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count = count-4*wcount;
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while (wcount>0)
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{
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/* Adjust to read within 4K block boundaries */
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blocksize = (0x1000-(0xFFF&address))>>2;
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if (wcount<blocksize)
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blocksize = wcount;
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ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
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for (writecount=0; writecount<blocksize; writecount++)
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{
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ahbap_write_reg(swjdp, AHBAP_DRW, buffer+4*writecount );
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}
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if (swjdp_transaction_endcheck(swjdp)==ERROR_OK)
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{
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wcount = wcount-blocksize;
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address = address+4*blocksize;
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buffer = buffer + 4*blocksize;
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}
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|
else
|
|
{
|
|
errorcount++;
|
|
}
|
|
if (errorcount>1)
|
|
{
|
|
WARNING("Block read error address %x, count %x", address, count);
|
|
return ERROR_JTAG_DEVICE_ERROR;
|
|
}
|
|
}
|
|
|
|
while (count>0)
|
|
{
|
|
ahbap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
|
|
outvalue = (*buffer++)<<8*(address&0x3) ;
|
|
ahbap_write_reg_u32(swjdp, AHBAP_DRW, outvalue );
|
|
retval = swjdp_transaction_endcheck(swjdp);
|
|
count--;
|
|
address++;
|
|
}
|
|
|
|
return retval;
|
|
}
|
|
|
|
/*****************************************************************************
|
|
* *
|
|
* ahbap_read_buf(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address) *
|
|
* *
|
|
* Read block fast in target order (little endian) into a buffer *
|
|
* *
|
|
*****************************************************************************/
|
|
int ahbap_read_buf(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
|
|
{
|
|
u32 invalue;
|
|
int wcount, blocksize, readcount, errorcount=0, retval=ERROR_OK;
|
|
|
|
swjdp->trans_mode = TRANS_MODE_COMPOSITE;
|
|
|
|
while ( (address&0x3)&&(count>0) )
|
|
{
|
|
ahbap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
|
|
ahbap_read_reg_u32(swjdp, AHBAP_DRW, &invalue );
|
|
swjdp_transaction_endcheck(swjdp);
|
|
*buffer++ = (invalue>>8*(address&0x3))&0xFF;
|
|
count--;
|
|
address++;
|
|
}
|
|
wcount = count>>2;
|
|
count = count-4*wcount;
|
|
while (wcount>0)
|
|
{
|
|
/* Adjust to read within 4K block boundaries */
|
|
blocksize = (0x1000-(0xFFF&address))>>2;
|
|
if (wcount<blocksize)
|
|
blocksize = wcount;
|
|
ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
|
|
/* Scan out first read */
|
|
swjdp_scan(swjdp->jtag_info, SWJDP_IR_APACC, AHBAP_DRW, DPAP_READ, 0, NULL, NULL);
|
|
for (readcount=0; readcount<blocksize-1; readcount++)
|
|
{
|
|
/* Scan out read instruction and scan in previous value */
|
|
swjdp_scan(swjdp->jtag_info, SWJDP_IR_APACC, AHBAP_DRW, DPAP_READ, 0, buffer+4*readcount, &swjdp->ack);
|
|
}
|
|
/* Scan in last value */
|
|
swjdp_scan(swjdp->jtag_info, SWJDP_IR_DPACC, 0xC, DPAP_READ, 0, buffer+4*readcount, &swjdp->ack);
|
|
if (swjdp_transaction_endcheck(swjdp)==ERROR_OK)
|
|
{
|
|
wcount = wcount-blocksize;
|
|
address += 4*blocksize;
|
|
buffer += 4*blocksize;
|
|
}
|
|
else
|
|
{
|
|
errorcount++;
|
|
}
|
|
if (errorcount>1)
|
|
{
|
|
WARNING("Block read error address %x, count %x", address, count);
|
|
return ERROR_JTAG_DEVICE_ERROR;
|
|
}
|
|
}
|
|
|
|
while (count>0)
|
|
{
|
|
ahbap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
|
|
ahbap_read_reg_u32(swjdp, AHBAP_DRW, &invalue );
|
|
retval = swjdp_transaction_endcheck(swjdp);
|
|
*buffer++ = (invalue>>8*(address&0x3))&0xFF;
|
|
count--;
|
|
address++;
|
|
}
|
|
|
|
return retval;
|
|
}
|
|
|
|
int ahbap_block_read_u32(swjdp_common_t *swjdp, u32 *buffer, int count, u32 address)
|
|
{
|
|
int readcount, errorcount=0;
|
|
u32 blockmax, blocksize;
|
|
|
|
swjdp->trans_mode = TRANS_MODE_COMPOSITE;
|
|
|
|
while (count>0)
|
|
{
|
|
/* Adjust to read within 4K block boundaries */
|
|
blocksize = (0x1000-(0xFFF&address))>>2;
|
|
if (count<blocksize)
|
|
blocksize = count;
|
|
ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
|
|
for (readcount=0; readcount<blocksize; readcount++)
|
|
{
|
|
ahbap_read_reg_u32(swjdp, AHBAP_DRW, buffer+readcount );
|
|
}
|
|
if (swjdp_transaction_endcheck(swjdp)==ERROR_OK)
|
|
{
|
|
count = count-blocksize;
|
|
address = address+4*blocksize;
|
|
buffer = buffer + blocksize;
|
|
}
|
|
else
|
|
{
|
|
errorcount++;
|
|
}
|
|
if (errorcount>1)
|
|
{
|
|
WARNING("Block read error address %x, count %x", address, count);
|
|
return ERROR_JTAG_DEVICE_ERROR;
|
|
}
|
|
}
|
|
|
|
return ERROR_OK;
|
|
}
|
|
|
|
int ahbap_read_coreregister_u32(swjdp_common_t *swjdp, u32 *value, int regnum)
|
|
{
|
|
swjdp->trans_mode = TRANS_MODE_COMPOSITE;
|
|
|
|
/* ahbap_write_system_u32(swjdp, DCB_DCRSR, regnum); */
|
|
ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR&0xFFFFFFF0);
|
|
ahbap_write_reg_u32(swjdp, AHBAP_BD0|DCB_DCRSR&0xC, regnum );
|
|
|
|
/* ahbap_read_system_u32(swjdp, DCB_DCRDR, value); */
|
|
ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR&0xFFFFFFF0);
|
|
ahbap_read_reg_u32(swjdp, AHBAP_BD0|DCB_DCRDR&0xC, value );
|
|
|
|
return swjdp_transaction_endcheck(swjdp);
|
|
}
|
|
|
|
int ahbap_write_coreregister_u32(swjdp_common_t *swjdp, u32 value, int regnum)
|
|
{
|
|
swjdp->trans_mode = TRANS_MODE_COMPOSITE;
|
|
|
|
/* ahbap_write_system_u32(swjdp, DCB_DCRDR, core_regs[i]); */
|
|
ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR&0xFFFFFFF0);
|
|
ahbap_write_reg_u32(swjdp, AHBAP_BD0|DCB_DCRDR&0xC, value );
|
|
|
|
/* ahbap_write_system_u32(swjdp, DCB_DCRSR, i | DCRSR_WnR ); */
|
|
ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR&0xFFFFFFF0);
|
|
ahbap_write_reg_u32(swjdp, AHBAP_BD0|DCB_DCRSR&0xC, regnum | DCRSR_WnR );
|
|
|
|
return swjdp_transaction_endcheck(swjdp);
|
|
}
|
|
|
|
int ahbap_debugport_init(swjdp_common_t *swjdp)
|
|
{
|
|
|
|
u32 idreg, romaddr, dummy;
|
|
u32 ctrlstat;
|
|
int cnt=0;
|
|
DEBUG("");
|
|
swjdp->ap_csw_value = -1;
|
|
swjdp->ap_tar_value = -1;
|
|
swjdp->trans_mode = TRANS_MODE_ATOMIC;
|
|
swjdp_read_dpacc(swjdp, &dummy, DP_CTRL_STAT);
|
|
swjdp_write_dpacc(swjdp, SSTICKYERR, DP_CTRL_STAT);
|
|
swjdp_read_dpacc(swjdp, &dummy, DP_CTRL_STAT);
|
|
|
|
swjdp->dp_ctrl_stat = CDBGPWRUPREQ|CSYSPWRUPREQ;
|
|
|
|
swjdp_write_dpacc(swjdp, swjdp->dp_ctrl_stat, DP_CTRL_STAT);
|
|
swjdp_read_dpacc(swjdp, &ctrlstat, DP_CTRL_STAT);
|
|
jtag_execute_queue();
|
|
|
|
/* Check that we have debug power domains activated */
|
|
while (!(ctrlstat & CDBGPWRUPACK) && (cnt++<10))
|
|
{
|
|
DEBUG(" swjdp: wait CDBGPWRUPACK");
|
|
swjdp_read_dpacc(swjdp, &ctrlstat, DP_CTRL_STAT);
|
|
jtag_execute_queue();
|
|
|
|
usleep(10000);
|
|
}
|
|
|
|
while (!(ctrlstat & CSYSPWRUPACK) && (cnt++<10))
|
|
{
|
|
DEBUG(" swjdp: wait CSYSPWRUPACK");
|
|
swjdp_read_dpacc(swjdp, &ctrlstat, DP_CTRL_STAT);
|
|
jtag_execute_queue();
|
|
usleep(10000);
|
|
}
|
|
|
|
|
|
swjdp_read_dpacc(swjdp, &dummy, DP_CTRL_STAT);
|
|
/* With debug power on we can activate OVERRUN checking */
|
|
swjdp->dp_ctrl_stat = CDBGPWRUPREQ|CSYSPWRUPREQ|CORUNDETECT;
|
|
swjdp_write_dpacc(swjdp, swjdp->dp_ctrl_stat , DP_CTRL_STAT);
|
|
swjdp_read_dpacc(swjdp, &dummy, DP_CTRL_STAT);
|
|
|
|
ahbap_read_reg_u32(swjdp, 0xFC, &idreg );
|
|
ahbap_read_reg_u32(swjdp, 0xF8, &romaddr );
|
|
|
|
DEBUG("AHB-AP ID Register 0x%x, Debug ROM Address 0x%x",idreg,romaddr);
|
|
|
|
return ERROR_OK;
|
|
}
|