145 lines
4.0 KiB
INI
145 lines
4.0 KiB
INI
# SPDX-License-Identifier: GPL-2.0-or-later
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# script for stm32f4x family
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#
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# stm32f4 devices support both JTAG and SWD transports.
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#
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source [find target/swj-dp.tcl]
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source [find mem_helper.tcl]
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME stm32f4x
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}
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set _ENDIAN little
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# Work-area is a space in RAM used for flash programming
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# By default use 32kB (Available RAM in smallest device STM32F410)
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if { [info exists WORKAREASIZE] } {
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set _WORKAREASIZE $WORKAREASIZE
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} else {
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set _WORKAREASIZE 0x8000
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}
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#jtag scan chain
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if { [info exists CPUTAPID] } {
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set _CPUTAPID $CPUTAPID
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} else {
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if { [using_jtag] } {
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# See STM Document RM0090
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# Section 38.6.3 - corresponds to Cortex-M4 r0p1
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set _CPUTAPID 0x4ba00477
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} {
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set _CPUTAPID 0x2ba01477
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}
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}
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swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
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dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
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if {[using_jtag]} {
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jtag newtap $_CHIPNAME bs -irlen 5
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}
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
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$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
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set _FLASHNAME $_CHIPNAME.flash
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flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME
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flash bank $_CHIPNAME.otp stm32f2x 0x1fff7800 0 0 0 $_TARGETNAME
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if { [info exists QUADSPI] && $QUADSPI } {
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set a [llength [flash list]]
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set _QSPINAME $_CHIPNAME.qspi
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flash bank $_QSPINAME stmqspi 0x90000000 0 0 0 $_TARGETNAME 0xA0001000
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}
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# JTAG speed should be <= F_CPU/6. F_CPU after reset is 16MHz, so use F_JTAG = 2MHz
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#
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# Since we may be running of an RC oscilator, we crank down the speed a
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# bit more to be on the safe side. Perhaps superstition, but if are
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# running off a crystal, we can run closer to the limit. Note
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# that there can be a pretty wide band where things are more or less stable.
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adapter speed 2000
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adapter srst delay 100
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if {[using_jtag]} {
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jtag_ntrst_delay 100
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}
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reset_config srst_nogate
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if {![using_hla]} {
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# if srst is not fitted use SYSRESETREQ to
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# perform a soft reset
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cortex_m reset_config sysresetreq
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}
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$_TARGETNAME configure -event examine-end {
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# Enable debug during low power modes (uses more power)
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# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
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mmw 0xE0042004 0x00000007 0
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# Stop watchdog counters during halt
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# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
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mmw 0xE0042008 0x00001800 0
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}
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tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000
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lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu
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proc _proc_pre_enable_$_CHIPNAME.tpiu {_chipname} {
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targets $_chipname.cpu
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if { [$_chipname.tpiu cget -protocol] eq "sync" } {
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switch [$_chipname.tpiu cget -port-width] {
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1 {
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mmw 0xE0042004 0x00000060 0x000000c0
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mmw 0x40021020 0x00000000 0x0000ff00
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mmw 0x40021000 0x000000a0 0x000000f0
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mmw 0x40021008 0x000000f0 0x00000000
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}
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2 {
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mmw 0xE0042004 0x000000a0 0x000000c0
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mmw 0x40021020 0x00000000 0x000fff00
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mmw 0x40021000 0x000002a0 0x000003f0
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mmw 0x40021008 0x000003f0 0x00000000
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}
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4 {
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mmw 0xE0042004 0x000000e0 0x000000c0
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mmw 0x40021020 0x00000000 0x0fffff00
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mmw 0x40021000 0x00002aa0 0x00003ff0
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mmw 0x40021008 0x00003ff0 0x00000000
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}
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}
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} else {
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mmw 0xE0042004 0x00000020 0x000000c0
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}
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}
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$_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu $_CHIPNAME"
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$_TARGETNAME configure -event reset-init {
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# Configure PLL to boost clock to HSI x 4 (64 MHz)
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mww 0x40023804 0x08012008 ;# RCC_PLLCFGR 16 Mhz /8 (M) * 128 (N) /4(P)
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mww 0x40023C00 0x00000102 ;# FLASH_ACR = PRFTBE | 2(Latency)
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mmw 0x40023800 0x01000000 0 ;# RCC_CR |= PLLON
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sleep 10 ;# Wait for PLL to lock
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mmw 0x40023808 0x00001000 0 ;# RCC_CFGR |= RCC_CFGR_PPRE1_DIV2
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mmw 0x40023808 0x00000002 0 ;# RCC_CFGR |= RCC_CFGR_SW_PLL
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# Boost JTAG frequency
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adapter speed 8000
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}
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$_TARGETNAME configure -event reset-start {
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# Reduce speed since CPU speed will slow down to 16MHz with the reset
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adapter speed 2000
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}
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