162 lines
4.5 KiB
INI
162 lines
4.5 KiB
INI
# SPDX-License-Identifier: GPL-2.0-or-later
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# common script for stm32l5x and stm32u5x families
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# Work-area is a space in RAM used for flash programming
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# By default use 64kB
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if { [info exists WORKAREASIZE] } {
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set _WORKAREASIZE $WORKAREASIZE
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} else {
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set _WORKAREASIZE 0x10000
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}
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#jtag scan chain
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if { [info exists CPUTAPID] } {
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set _CPUTAPID $CPUTAPID
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} else {
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if { [using_jtag] } {
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# STM32L5x: RM0438 Rev5, Section 52.2.8 JTAG debug port - Table 425. JTAG-DP data registers
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# STM32U5x: RM0456 Rev1, Section 65.2.8 JTAG debug port - Table 661. JTAG-DP data registers
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# Corresponds to Cortex®-M33 JTAG debug port ID code
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set _CPUTAPID 0x0ba04477
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} {
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# SWD IDCODE (single drop, arm)
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set _CPUTAPID 0x0be12477
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}
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}
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swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
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dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
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if {[using_jtag]} {
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jtag newtap $_CHIPNAME bs -irlen 5
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}
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap
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# use non-secure RAM by default
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$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
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# create sec/ns flash and otp memories (sizes will be probed)
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flash bank $_CHIPNAME.flash_ns stm32l4x 0x08000000 0 0 0 $_TARGETNAME
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flash bank $_CHIPNAME.flash_alias_s stm32l4x 0x0C000000 0 0 0 $_TARGETNAME
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flash bank $_CHIPNAME.otp stm32l4x 0x0BFA0000 0 0 0 $_TARGETNAME
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# Common knowledge tells JTAG speed should be <= F_CPU/6.
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# F_CPU after reset is MSI 4MHz, so use F_JTAG = 500 kHz to stay on
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# the safe side.
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#
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# Note that there is a pretty wide band where things are
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# more or less stable, see http://review.openocd.org/3366
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adapter speed 500
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adapter srst delay 100
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if {[using_jtag]} {
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jtag_ntrst_delay 100
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}
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reset_config srst_nogate
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if {![using_hla]} {
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# if srst is not fitted use SYSRESETREQ to
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# perform a soft reset
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cortex_m reset_config sysresetreq
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}
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proc stm32x5x_is_secure {} {
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# read Debug Security Control and Status Register (DSCSR) and check CDS (bit 16)
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set DSCSR [mrw 0xE000EE08]
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return [expr {($DSCSR & (1 << 16)) != 0}]
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}
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proc stm32x5x_ahb_ap_non_secure_access {} {
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# SPROT=1=Non Secure access, Priv=1
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[[target current] cget -dap] apcsw 0x4B000000 0x4F000000
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}
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proc stm32x5x_ahb_ap_secure_access {} {
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# SPROT=0=Secure access, Priv=1
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[[target current] cget -dap] apcsw 0x0B000000 0x4F000000
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}
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$_TARGETNAME configure -event reset-start {
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# Reset clock is MSI (4 MHz)
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adapter speed 480
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}
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$_TARGETNAME configure -event examine-end {
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# DBGMCU_CR |= DBG_STANDBY | DBG_STOP
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mmw 0xE0044004 0x00000006 0
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# Stop watchdog counters during halt
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# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
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mmw 0xE0044008 0x00001800 0
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}
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$_TARGETNAME configure -event halted {
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set secure [stm32x5x_is_secure]
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if {$secure} {
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set secure_str "Secure"
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stm32x5x_ahb_ap_secure_access
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} else {
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set secure_str "Non-Secure"
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stm32x5x_ahb_ap_non_secure_access
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}
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# print the secure state only when it changes
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set _TARGETNAME [target current]
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global $_TARGETNAME.secure
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if {![info exists $_TARGETNAME.secure] || $secure != [set $_TARGETNAME.secure]} {
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echo "CPU in $secure_str state"
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# update saved security state
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set $_TARGETNAME.secure $secure
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}
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}
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$_TARGETNAME configure -event gdb-flash-erase-start {
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set use_secure_workarea 0
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# check if FLASH_OPTR.TZEN is enabled
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set FLASH_OPTR [mrw 0x40022040]
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if {[expr {$FLASH_OPTR & 0x80000000}] == 0} {
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echo "TZEN option bit disabled"
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stm32x5x_ahb_ap_non_secure_access
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} else {
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stm32x5x_ahb_ap_secure_access
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echo "TZEN option bit enabled"
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# check if FLASH_OPTR.RDP is not Level 0.5
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if {[expr {$FLASH_OPTR & 0xFF}] != 0x55} {
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set use_secure_workarea 1
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}
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}
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set _TARGETNAME [target current]
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set workarea_addr [$_TARGETNAME cget -work-area-phys]
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echo "workarea_addr $workarea_addr"
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if {$use_secure_workarea} {
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set workarea_addr [expr {$workarea_addr | 0x10000000}]
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} else {
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set workarea_addr [expr {$workarea_addr & ~0x10000000}]
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}
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$_TARGETNAME configure -work-area-phys $workarea_addr
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}
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tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000
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lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu
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proc _proc_pre_enable_$_CHIPNAME.tpiu {_targetname} {
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targets $_targetname
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# Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
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# change this value accordingly to configure trace pins
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# assignment
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mmw 0xE0044004 0x00000020 0
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}
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$_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu $_TARGETNAME"
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