534 lines
14 KiB
C
534 lines
14 KiB
C
/***************************************************************************
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* Copyright (C) 2013 by Paul Fertser, fercerpav@gmail.com *
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* *
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* Copyright (C) 2012 by Creative Product Design, marc @ cpdesign.com.au *
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* Based on at91rm9200.c (c) Anders Larsen *
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* and RPi GPIO examples by Gert van Loo & Dom *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, write to the *
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* Free Software Foundation, Inc., *
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
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***************************************************************************/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include <jtag/interface.h>
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#include "bitbang.h"
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#include <sys/mman.h>
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uint32_t bcm2835_peri_base = 0x20000000;
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#define BCM2835_GPIO_BASE (bcm2835_peri_base + 0x200000) /* GPIO controller */
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#define BCM2835_PADS_GPIO_0_27 (bcm2835_peri_base + 0x100000)
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#define BCM2835_PADS_GPIO_0_27_OFFSET (0x2c / 4)
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/* GPIO setup macros */
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#define MODE_GPIO(g) (*(pio_base+((g)/10))>>(((g)%10)*3) & 7)
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#define INP_GPIO(g) do { *(pio_base+((g)/10)) &= ~(7<<(((g)%10)*3)); } while (0)
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#define SET_MODE_GPIO(g, m) do { /* clear the mode bits first, then set as necessary */ \
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INP_GPIO(g); \
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*(pio_base+((g)/10)) |= ((m)<<(((g)%10)*3)); } while (0)
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#define OUT_GPIO(g) SET_MODE_GPIO(g, 1)
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#define GPIO_SET (*(pio_base+7)) /* sets bits which are 1, ignores bits which are 0 */
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#define GPIO_CLR (*(pio_base+10)) /* clears bits which are 1, ignores bits which are 0 */
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#define GPIO_LEV (*(pio_base+13)) /* current level of the pin */
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static int dev_mem_fd;
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static volatile uint32_t *pio_base;
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static int bcm2835gpio_read(void);
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static void bcm2835gpio_write(int tck, int tms, int tdi);
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static void bcm2835gpio_reset(int trst, int srst);
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static int bcm2835_swdio_read(void);
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static void bcm2835_swdio_drive(bool is_output);
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static int bcm2835gpio_init(void);
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static int bcm2835gpio_quit(void);
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static struct bitbang_interface bcm2835gpio_bitbang = {
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.read = bcm2835gpio_read,
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.write = bcm2835gpio_write,
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.reset = bcm2835gpio_reset,
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.swdio_read = bcm2835_swdio_read,
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.swdio_drive = bcm2835_swdio_drive,
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.blink = NULL
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};
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/* GPIO numbers for each signal. Negative values are invalid */
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static int tck_gpio = -1;
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static int tck_gpio_mode;
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static int tms_gpio = -1;
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static int tms_gpio_mode;
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static int tdi_gpio = -1;
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static int tdi_gpio_mode;
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static int tdo_gpio = -1;
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static int tdo_gpio_mode;
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static int trst_gpio = -1;
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static int trst_gpio_mode;
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static int srst_gpio = -1;
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static int srst_gpio_mode;
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static int swclk_gpio = -1;
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static int swclk_gpio_mode;
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static int swdio_gpio = -1;
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static int swdio_gpio_mode;
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/* Transition delay coefficients */
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static int speed_coeff = 113714;
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static int speed_offset = 28;
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static unsigned int jtag_delay;
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static int bcm2835gpio_read(void)
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{
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return !!(GPIO_LEV & 1<<tdo_gpio);
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}
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static void bcm2835gpio_write(int tck, int tms, int tdi)
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{
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uint32_t set = tck<<tck_gpio | tms<<tms_gpio | tdi<<tdi_gpio;
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uint32_t clear = !tck<<tck_gpio | !tms<<tms_gpio | !tdi<<tdi_gpio;
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GPIO_SET = set;
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GPIO_CLR = clear;
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for (unsigned int i = 0; i < jtag_delay; i++)
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asm volatile ("");
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}
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static void bcm2835gpio_swd_write(int tck, int tms, int tdi)
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{
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uint32_t set = tck<<swclk_gpio | tdi<<swdio_gpio;
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uint32_t clear = !tck<<swclk_gpio | !tdi<<swdio_gpio;
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GPIO_SET = set;
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GPIO_CLR = clear;
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for (unsigned int i = 0; i < jtag_delay; i++)
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asm volatile ("");
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}
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/* (1) assert or (0) deassert reset lines */
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static void bcm2835gpio_reset(int trst, int srst)
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{
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uint32_t set = 0;
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uint32_t clear = 0;
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if (trst_gpio > 0) {
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set |= !trst<<trst_gpio;
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clear |= trst<<trst_gpio;
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}
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if (srst_gpio > 0) {
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set |= !srst<<srst_gpio;
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clear |= srst<<srst_gpio;
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}
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GPIO_SET = set;
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GPIO_CLR = clear;
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}
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static void bcm2835_swdio_drive(bool is_output)
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{
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if (is_output)
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OUT_GPIO(swdio_gpio);
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else
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INP_GPIO(swdio_gpio);
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}
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static int bcm2835_swdio_read(void)
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{
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return !!(GPIO_LEV & 1 << swdio_gpio);
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}
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static int bcm2835gpio_khz(int khz, int *jtag_speed)
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{
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if (!khz) {
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LOG_DEBUG("RCLK not supported");
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return ERROR_FAIL;
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}
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*jtag_speed = speed_coeff/khz - speed_offset;
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if (*jtag_speed < 0)
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*jtag_speed = 0;
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return ERROR_OK;
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}
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static int bcm2835gpio_speed_div(int speed, int *khz)
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{
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*khz = speed_coeff/(speed + speed_offset);
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return ERROR_OK;
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}
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static int bcm2835gpio_speed(int speed)
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{
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jtag_delay = speed;
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return ERROR_OK;
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}
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static int is_gpio_valid(int gpio)
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{
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return gpio >= 0 && gpio <= 53;
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}
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COMMAND_HANDLER(bcm2835gpio_handle_jtag_gpionums)
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{
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if (CMD_ARGC == 4) {
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COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], tck_gpio);
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COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], tms_gpio);
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COMMAND_PARSE_NUMBER(int, CMD_ARGV[2], tdi_gpio);
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COMMAND_PARSE_NUMBER(int, CMD_ARGV[3], tdo_gpio);
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} else if (CMD_ARGC != 0) {
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return ERROR_COMMAND_SYNTAX_ERROR;
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}
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command_print(CMD_CTX,
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"BCM2835 GPIO config: tck = %d, tms = %d, tdi = %d, tdo = %d",
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tck_gpio, tms_gpio, tdi_gpio, tdo_gpio);
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return ERROR_OK;
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}
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COMMAND_HANDLER(bcm2835gpio_handle_jtag_gpionum_tck)
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{
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if (CMD_ARGC == 1)
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COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], tck_gpio);
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command_print(CMD_CTX, "BCM2835 GPIO config: tck = %d", tck_gpio);
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return ERROR_OK;
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}
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COMMAND_HANDLER(bcm2835gpio_handle_jtag_gpionum_tms)
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{
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if (CMD_ARGC == 1)
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COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], tms_gpio);
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command_print(CMD_CTX, "BCM2835 GPIO config: tms = %d", tms_gpio);
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return ERROR_OK;
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}
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COMMAND_HANDLER(bcm2835gpio_handle_jtag_gpionum_tdo)
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{
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if (CMD_ARGC == 1)
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COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], tdo_gpio);
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command_print(CMD_CTX, "BCM2835 GPIO config: tdo = %d", tdo_gpio);
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return ERROR_OK;
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}
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COMMAND_HANDLER(bcm2835gpio_handle_jtag_gpionum_tdi)
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{
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if (CMD_ARGC == 1)
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COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], tdi_gpio);
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command_print(CMD_CTX, "BCM2835 GPIO config: tdi = %d", tdi_gpio);
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return ERROR_OK;
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}
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COMMAND_HANDLER(bcm2835gpio_handle_jtag_gpionum_srst)
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{
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if (CMD_ARGC == 1)
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COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], srst_gpio);
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command_print(CMD_CTX, "BCM2835 GPIO config: srst = %d", srst_gpio);
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return ERROR_OK;
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}
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COMMAND_HANDLER(bcm2835gpio_handle_jtag_gpionum_trst)
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{
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if (CMD_ARGC == 1)
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COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], trst_gpio);
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command_print(CMD_CTX, "BCM2835 GPIO config: trst = %d", trst_gpio);
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return ERROR_OK;
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}
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COMMAND_HANDLER(bcm2835gpio_handle_swd_gpionums)
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{
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if (CMD_ARGC == 2) {
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COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], swclk_gpio);
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COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], swdio_gpio);
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} else if (CMD_ARGC != 0) {
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return ERROR_COMMAND_SYNTAX_ERROR;
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}
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command_print(CMD_CTX,
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"BCM2835 GPIO nums: swclk = %d, swdio = %d",
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swclk_gpio, swdio_gpio);
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return ERROR_OK;
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}
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COMMAND_HANDLER(bcm2835gpio_handle_swd_gpionum_swclk)
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{
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if (CMD_ARGC == 1)
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COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], swclk_gpio);
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command_print(CMD_CTX, "BCM2835 num: swclk = %d", swclk_gpio);
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return ERROR_OK;
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}
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COMMAND_HANDLER(bcm2835gpio_handle_swd_gpionum_swdio)
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{
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if (CMD_ARGC == 1)
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COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], swdio_gpio);
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command_print(CMD_CTX, "BCM2835 num: swdio = %d", swdio_gpio);
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return ERROR_OK;
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}
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COMMAND_HANDLER(bcm2835gpio_handle_speed_coeffs)
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{
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if (CMD_ARGC == 2) {
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COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], speed_coeff);
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COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], speed_offset);
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}
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return ERROR_OK;
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}
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COMMAND_HANDLER(bcm2835gpio_handle_peripheral_base)
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{
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if (CMD_ARGC == 1)
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COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], bcm2835_peri_base);
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return ERROR_OK;
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}
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static const struct command_registration bcm2835gpio_command_handlers[] = {
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{
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.name = "bcm2835gpio_jtag_nums",
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.handler = &bcm2835gpio_handle_jtag_gpionums,
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.mode = COMMAND_CONFIG,
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.help = "gpio numbers for tck, tms, tdi, tdo. (in that order)",
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.usage = "(tck tms tdi tdo)* ",
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},
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{
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.name = "bcm2835gpio_tck_num",
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.handler = &bcm2835gpio_handle_jtag_gpionum_tck,
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.mode = COMMAND_CONFIG,
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.help = "gpio number for tck.",
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},
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{
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.name = "bcm2835gpio_tms_num",
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.handler = &bcm2835gpio_handle_jtag_gpionum_tms,
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.mode = COMMAND_CONFIG,
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.help = "gpio number for tms.",
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},
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{
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.name = "bcm2835gpio_tdo_num",
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.handler = &bcm2835gpio_handle_jtag_gpionum_tdo,
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.mode = COMMAND_CONFIG,
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.help = "gpio number for tdo.",
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},
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{
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.name = "bcm2835gpio_tdi_num",
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.handler = &bcm2835gpio_handle_jtag_gpionum_tdi,
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.mode = COMMAND_CONFIG,
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.help = "gpio number for tdi.",
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},
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{
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.name = "bcm2835gpio_swd_nums",
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.handler = &bcm2835gpio_handle_swd_gpionums,
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.mode = COMMAND_CONFIG,
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.help = "gpio numbers for swclk, swdio. (in that order)",
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.usage = "(swclk swdio)* ",
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},
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{
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.name = "bcm2835gpio_swclk_num",
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.handler = &bcm2835gpio_handle_swd_gpionum_swclk,
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.mode = COMMAND_CONFIG,
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.help = "gpio number for swclk.",
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},
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{
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.name = "bcm2835gpio_swdio_num",
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.handler = &bcm2835gpio_handle_swd_gpionum_swdio,
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.mode = COMMAND_CONFIG,
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.help = "gpio number for swdio.",
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},
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{
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.name = "bcm2835gpio_srst_num",
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.handler = &bcm2835gpio_handle_jtag_gpionum_srst,
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.mode = COMMAND_CONFIG,
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.help = "gpio number for srst.",
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},
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{
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.name = "bcm2835gpio_trst_num",
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.handler = &bcm2835gpio_handle_jtag_gpionum_trst,
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.mode = COMMAND_CONFIG,
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.help = "gpio number for trst.",
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},
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{
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.name = "bcm2835gpio_speed_coeffs",
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.handler = &bcm2835gpio_handle_speed_coeffs,
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.mode = COMMAND_CONFIG,
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.help = "SPEED_COEFF and SPEED_OFFSET for delay calculations.",
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},
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{
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.name = "bcm2835gpio_peripheral_base",
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.handler = &bcm2835gpio_handle_peripheral_base,
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.mode = COMMAND_CONFIG,
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.help = "peripheral base to access GPIOs (RPi1 0x20000000, RPi2 0x3F000000).",
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},
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COMMAND_REGISTRATION_DONE
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};
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static const char * const bcm2835_transports[] = { "jtag", "swd", NULL };
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struct jtag_interface bcm2835gpio_interface = {
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.name = "bcm2835gpio",
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.supported = DEBUG_CAP_TMS_SEQ,
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.execute_queue = bitbang_execute_queue,
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.transports = bcm2835_transports,
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.swd = &bitbang_swd,
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.speed = bcm2835gpio_speed,
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.khz = bcm2835gpio_khz,
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.speed_div = bcm2835gpio_speed_div,
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.commands = bcm2835gpio_command_handlers,
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.init = bcm2835gpio_init,
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.quit = bcm2835gpio_quit,
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};
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static bool bcm2835gpio_jtag_mode_possible(void)
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{
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if (!is_gpio_valid(tck_gpio))
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return 0;
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if (!is_gpio_valid(tms_gpio))
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return 0;
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if (!is_gpio_valid(tdi_gpio))
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return 0;
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if (!is_gpio_valid(tdo_gpio))
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return 0;
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return 1;
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}
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static bool bcm2835gpio_swd_mode_possible(void)
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{
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if (!is_gpio_valid(swclk_gpio))
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return 0;
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if (!is_gpio_valid(swdio_gpio))
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return 0;
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return 1;
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}
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static int bcm2835gpio_init(void)
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{
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bitbang_interface = &bcm2835gpio_bitbang;
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LOG_INFO("BCM2835 GPIO JTAG/SWD bitbang driver");
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if (bcm2835gpio_jtag_mode_possible()) {
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if (bcm2835gpio_swd_mode_possible())
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LOG_INFO("JTAG and SWD modes enabled");
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else
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LOG_INFO("JTAG only mode enabled (specify swclk and swdio gpio to add SWD mode)");
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if (!is_gpio_valid(trst_gpio) && !is_gpio_valid(srst_gpio)) {
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LOG_ERROR("Require at least one of trst or srst gpios to be specified");
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return ERROR_JTAG_INIT_FAILED;
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}
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} else if (bcm2835gpio_swd_mode_possible()) {
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LOG_INFO("SWD only mode enabled (specify tck, tms, tdi and tdo gpios to add JTAG mode)");
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} else {
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LOG_ERROR("Require tck, tms, tdi and tdo gpios for JTAG mode and/or swclk and swdio gpio for SWD mode");
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return ERROR_JTAG_INIT_FAILED;
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}
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dev_mem_fd = open("/dev/mem", O_RDWR | O_SYNC);
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if (dev_mem_fd < 0) {
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perror("open");
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return ERROR_JTAG_INIT_FAILED;
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}
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pio_base = mmap(NULL, sysconf(_SC_PAGE_SIZE), PROT_READ | PROT_WRITE,
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MAP_SHARED, dev_mem_fd, BCM2835_GPIO_BASE);
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if (pio_base == MAP_FAILED) {
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perror("mmap");
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close(dev_mem_fd);
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return ERROR_JTAG_INIT_FAILED;
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}
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static volatile uint32_t *pads_base;
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pads_base = mmap(NULL, sysconf(_SC_PAGE_SIZE), PROT_READ | PROT_WRITE,
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MAP_SHARED, dev_mem_fd, BCM2835_PADS_GPIO_0_27);
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if (pads_base == MAP_FAILED) {
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perror("mmap");
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close(dev_mem_fd);
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return ERROR_JTAG_INIT_FAILED;
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}
|
|
|
|
/* set 16mA drive strength */
|
|
pads_base[BCM2835_PADS_GPIO_0_27_OFFSET] = 0x5a000018 + 7;
|
|
|
|
tdo_gpio_mode = MODE_GPIO(tdo_gpio);
|
|
tdi_gpio_mode = MODE_GPIO(tdi_gpio);
|
|
tck_gpio_mode = MODE_GPIO(tck_gpio);
|
|
tms_gpio_mode = MODE_GPIO(tms_gpio);
|
|
swclk_gpio_mode = MODE_GPIO(swclk_gpio);
|
|
swdio_gpio_mode = MODE_GPIO(swdio_gpio);
|
|
/*
|
|
* Configure TDO as an input, and TDI, TCK, TMS, TRST, SRST
|
|
* as outputs. Drive TDI and TCK low, and TMS/TRST/SRST high.
|
|
*/
|
|
INP_GPIO(tdo_gpio);
|
|
|
|
GPIO_CLR = 1<<tdi_gpio | 1<<tck_gpio | 1<<swdio_gpio | 1<<swclk_gpio;
|
|
GPIO_SET = 1<<tms_gpio;
|
|
|
|
OUT_GPIO(tdi_gpio);
|
|
OUT_GPIO(tck_gpio);
|
|
OUT_GPIO(tms_gpio);
|
|
OUT_GPIO(swclk_gpio);
|
|
OUT_GPIO(swdio_gpio);
|
|
if (trst_gpio != -1) {
|
|
trst_gpio_mode = MODE_GPIO(trst_gpio);
|
|
GPIO_SET = 1 << trst_gpio;
|
|
OUT_GPIO(trst_gpio);
|
|
}
|
|
if (srst_gpio != -1) {
|
|
srst_gpio_mode = MODE_GPIO(srst_gpio);
|
|
GPIO_SET = 1 << srst_gpio;
|
|
OUT_GPIO(srst_gpio);
|
|
}
|
|
|
|
LOG_DEBUG("saved pinmux settings: tck %d tms %d tdi %d "
|
|
"tdo %d trst %d srst %d", tck_gpio_mode, tms_gpio_mode,
|
|
tdi_gpio_mode, tdo_gpio_mode, trst_gpio_mode, srst_gpio_mode);
|
|
|
|
if (swd_mode) {
|
|
bcm2835gpio_bitbang.write = bcm2835gpio_swd_write;
|
|
bitbang_switch_to_swd();
|
|
}
|
|
|
|
return ERROR_OK;
|
|
}
|
|
|
|
static int bcm2835gpio_quit(void)
|
|
{
|
|
SET_MODE_GPIO(tdo_gpio, tdo_gpio_mode);
|
|
SET_MODE_GPIO(tdi_gpio, tdi_gpio_mode);
|
|
SET_MODE_GPIO(tck_gpio, tck_gpio_mode);
|
|
SET_MODE_GPIO(tms_gpio, tms_gpio_mode);
|
|
SET_MODE_GPIO(swclk_gpio, swclk_gpio_mode);
|
|
SET_MODE_GPIO(swdio_gpio, swdio_gpio_mode);
|
|
if (trst_gpio != -1)
|
|
SET_MODE_GPIO(trst_gpio, trst_gpio_mode);
|
|
if (srst_gpio != -1)
|
|
SET_MODE_GPIO(srst_gpio, srst_gpio_mode);
|
|
|
|
return ERROR_OK;
|
|
}
|