219 lines
7.4 KiB
C
219 lines
7.4 KiB
C
/***************************************************************************
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* Copyright (C) 2009-2010 by David Brownell *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, write to the *
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* Free Software Foundation, Inc., *
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
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***************************************************************************/
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#ifndef SWD_H
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#define SWD_H
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#include <target/arm_adi_v5.h>
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/* Bits in SWD command packets, written from host to target
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* first bit on the wire is START
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*/
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#define SWD_CMD_START (1 << 0) /* always set */
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#define SWD_CMD_APnDP (1 << 1) /* set only for AP access */
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#define SWD_CMD_RnW (1 << 2) /* set only for read access */
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#define SWD_CMD_A32 (3 << 3) /* bits A[3:2] of register addr */
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#define SWD_CMD_PARITY (1 << 5) /* parity of APnDP|RnW|A32 */
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#define SWD_CMD_STOP (0 << 6) /* always clear for synch SWD */
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#define SWD_CMD_PARK (1 << 7) /* driven high by host */
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/* followed by TRN, 3-bits of ACK, TRN */
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/**
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* Construct a "cmd" byte, in lSB bit order, which swd_driver.read_reg()
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* and swd_driver.write_reg() methods will use directly.
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*/
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static inline uint8_t swd_cmd(bool is_read, bool is_ap, uint8_t regnum)
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{
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uint8_t cmd = (is_ap ? SWD_CMD_APnDP : 0)
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| (is_read ? SWD_CMD_RnW : 0)
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| ((regnum & 0xc) << 1);
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/* 8 cmd bits 4:1 may be set */
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if (parity_u32(cmd))
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cmd |= SWD_CMD_PARITY;
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/* driver handles START, STOP, and TRN */
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return cmd;
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}
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/* SWD_ACK_* bits are defined in <target/arm_adi_v5.h> */
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/**
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* Line reset.
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*
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* Line reset is at least 50 SWCLK cycles with SWDIO driven high, followed
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* by at least one idle (low) cycle.
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*/
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static const uint8_t swd_seq_line_reset[] = {
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x03
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};
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static const unsigned swd_seq_line_reset_len = 51;
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/**
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* JTAG-to-SWD sequence.
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*
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* The JTAG-to-SWD sequence is at least 50 TCK/SWCLK cycles with TMS/SWDIO
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* high, putting either interface logic into reset state, followed by a
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* specific 16-bit sequence and finally a line reset in case the SWJ-DP was
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* already in SWD mode.
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*/
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static const uint8_t swd_seq_jtag_to_swd[] = {
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7b, 0x9e,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x0f,
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};
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static const unsigned swd_seq_jtag_to_swd_len = 118;
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/**
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* SWD-to-JTAG sequence.
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*
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* The SWD-to-JTAG sequence is at least 50 TCK/SWCLK cycles with TMS/SWDIO
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* high, putting either interface logic into reset state, followed by a
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* specific 16-bit sequence and finally at least 5 TCK cycles to put the
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* JTAG TAP in TLR.
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*/
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static const uint8_t swd_seq_swd_to_jtag[] = {
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf3, 0x9c, 0xff
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};
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static const unsigned swd_seq_swd_to_jtag_len = 71;
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/**
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* SWD-to-dormant sequence.
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*
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* This is at least 50 SWCLK cycles with SWDIO high to put the interface
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* in reset state, followed by a specific 16-bit sequence.
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*/
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static const uint8_t swd_seq_swd_to_dormant[] = {
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf3, 0x8e, 0x03
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};
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static const unsigned swd_seq_swd_to_dormant_len = 66;
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/**
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* Dormant-to-SWD sequence.
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*
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* This is at least 8 TCK/SWCLK cycles with TMS/SWDIO high to abort any ongoing
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* selection alert sequence, followed by a specific 128-bit selection alert
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* sequence, followed by 4 TCK/SWCLK cycles with TMS/SWDIO low, followed by
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* a specific protocol-dependent activation code. For SWD the activation code
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* is an 8-bit sequence. The sequence ends with a line reset.
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*/
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static const uint8_t swd_seq_dormant_to_swd[] = {
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0xff,
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0x92, 0xf3, 0x09, 0x62, 0x95, 0x2d, 0x85, 0x86,
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0xe9, 0xaf, 0xdd, 0xe3, 0xa2, 0x0e, 0xbc, 0x19,
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0x10, 0xfa, 0xff, 0xff, 0xff, 0xff, 0xff, 0x3f
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};
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static const unsigned swd_seq_dormant_to_swd_len = 199;
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enum swd_special_seq {
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LINE_RESET,
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JTAG_TO_SWD,
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SWD_TO_JTAG,
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SWD_TO_DORMANT,
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DORMANT_TO_SWD,
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};
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struct swd_driver {
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/**
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* Initialize the debug link so it can perform SWD operations.
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*
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* As an example, this would switch a dual-mode debug adapter
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* into SWD mode and out of JTAG mode.
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*
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* @return ERROR_OK on success, else a negative fault code.
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*/
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int (*init)(void);
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/**
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* Set the SWCLK frequency of the SWD link.
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*
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* The driver should round the desired value, downwards if possible, to
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* the nearest supported frequency. A negative value should be ignored
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* and can be used to query the current setting. If the driver does not
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* support a variable frequency a fixed, nominal, value should be
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* returned.
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*
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* If the frequency is increased, it must not apply before the currently
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* queued transactions are executed. If the frequency is lowered, it may
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* apply immediately.
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*
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* @param hz The desired frequency in Hz.
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* @return The actual resulting frequency after rounding.
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*/
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int_least32_t (*frequency)(int_least32_t hz);
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/**
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* Queue a special SWDIO sequence.
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*
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* @param seq The special sequence to generate.
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* @return ERROR_OK if the sequence was queued, negative error if the
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* sequence is unsupported.
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*/
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int (*switch_seq)(enum swd_special_seq seq);
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/**
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* Queued read of an AP or DP register.
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*
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* @param Command byte with APnDP/RnW/addr/parity bits
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* @param Where to store value to read from register
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* @param ap_delay_hint Number of idle cycles that may be
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* needed after an AP access to avoid WAITs
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*/
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void (*read_reg)(uint8_t cmd, uint32_t *value, uint32_t ap_delay_hint);
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/**
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* Queued write of an AP or DP register.
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*
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* @param Command byte with APnDP/RnW/addr/parity bits
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* @param Value to be written to the register
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* @param ap_delay_hint Number of idle cycles that may be
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* needed after an AP access to avoid WAITs
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*/
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void (*write_reg)(uint8_t cmd, uint32_t value, uint32_t ap_delay_hint);
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/**
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* Execute any queued transactions and collect the result.
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*
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* @return ERROR_OK on success, Ack response code on WAIT/FAULT
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* or negative error code on other kinds of failure.
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*/
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int (*run)(void);
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/**
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* Configures data collection from the Single-wire
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* trace (SWO) signal.
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* @param swo true if SWO data collection should be routed.
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*
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* For example, some debug adapters include a UART which
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* is normally connected to a microcontroller's UART TX,
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* but which may instead be connected to SWO for use in
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* collecting ITM (and possibly ETM) trace data.
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*
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* @return ERROR_OK on success, else a negative fault code.
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*/
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int *(*trace)(bool swo);
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};
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int swd_init_reset(struct command_context *cmd_ctx);
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void swd_add_reset(int req_srst);
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bool transport_is_swd(void);
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#endif /* SWD_H */
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