315 lines
9.3 KiB
C
315 lines
9.3 KiB
C
/*
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* Copyright (C) 2005 by Dominic Rath
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* Dominic.Rath@gmx.de
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*
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* Copyright (C) 2006 by Magnus Lundin
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* lundin@mlu.mine.nu
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*
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* Copyright (C) 2008 by Spencer Oliver
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* spen@spen-soft.co.uk
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*
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* Copyright (C) 2009 by Øyvind Harboe
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* oyvind.harboe@zylin.com
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the
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* Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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#ifndef __ARM_OPCODES_H
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#define __ARM_OPCODES_H
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/**
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* @file
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* Macros used to generate various ARM or Thumb opcodes.
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*/
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/* ARM mode instructions */
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/* Store multiple increment after
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* Rn: base register
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* List: for each bit in list: store register
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* S: in priviledged mode: store user-mode registers
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* W = 1: update the base register. W = 0: leave the base register untouched
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*/
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#define ARMV4_5_STMIA(Rn, List, S, W) \
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(0xe8800000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List))
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/* Load multiple increment after
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* Rn: base register
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* List: for each bit in list: store register
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* S: in priviledged mode: store user-mode registers
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* W = 1: update the base register. W = 0: leave the base register untouched
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*/
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#define ARMV4_5_LDMIA(Rn, List, S, W) \
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(0xe8900000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List))
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/* MOV r8, r8 */
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#define ARMV4_5_NOP (0xe1a08008)
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/* Move PSR to general purpose register
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* R = 1: SPSR R = 0: CPSR
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* Rn: target register
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*/
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#define ARMV4_5_MRS(Rn, R) (0xe10f0000 | ((R) << 22) | ((Rn) << 12))
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/* Store register
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* Rd: register to store
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* Rn: base register
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*/
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#define ARMV4_5_STR(Rd, Rn) (0xe5800000 | ((Rd) << 12) | ((Rn) << 16))
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/* Load register
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* Rd: register to load
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* Rn: base register
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*/
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#define ARMV4_5_LDR(Rd, Rn) (0xe5900000 | ((Rd) << 12) | ((Rn) << 16))
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/* Move general purpose register to PSR
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* R = 1: SPSR R = 0: CPSR
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* Field: Field mask
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* 1: control field 2: extension field 4: status field 8: flags field
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* Rm: source register
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*/
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#define ARMV4_5_MSR_GP(Rm, Field, R) \
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(0xe120f000 | (Rm) | ((Field) << 16) | ((R) << 22))
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#define ARMV4_5_MSR_IM(Im, Rotate, Field, R) \
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(0xe320f000 | (Im) | ((Rotate) << 8) | ((Field) << 16) | ((R) << 22))
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/* Load Register Word Immediate Post-Index
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* Rd: register to load
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* Rn: base register
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*/
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#define ARMV4_5_LDRW_IP(Rd, Rn) (0xe4900004 | ((Rd) << 12) | ((Rn) << 16))
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/* Load Register Halfword Immediate Post-Index
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* Rd: register to load
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* Rn: base register
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*/
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#define ARMV4_5_LDRH_IP(Rd, Rn) (0xe0d000b2 | ((Rd) << 12) | ((Rn) << 16))
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/* Load Register Byte Immediate Post-Index
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* Rd: register to load
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* Rn: base register
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*/
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#define ARMV4_5_LDRB_IP(Rd, Rn) (0xe4d00001 | ((Rd) << 12) | ((Rn) << 16))
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/* Store register Word Immediate Post-Index
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* Rd: register to store
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* Rn: base register
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*/
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#define ARMV4_5_STRW_IP(Rd, Rn) (0xe4800004 | ((Rd) << 12) | ((Rn) << 16))
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/* Store register Halfword Immediate Post-Index
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* Rd: register to store
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* Rn: base register
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*/
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#define ARMV4_5_STRH_IP(Rd, Rn) (0xe0c000b2 | ((Rd) << 12) | ((Rn) << 16))
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/* Store register Byte Immediate Post-Index
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* Rd: register to store
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* Rn: base register
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*/
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#define ARMV4_5_STRB_IP(Rd, Rn) (0xe4c00001 | ((Rd) << 12) | ((Rn) << 16))
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/* Branch (and Link)
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* Im: Branch target (left-shifted by 2 bits, added to PC)
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* L: 1: branch and link 0: branch only
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*/
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#define ARMV4_5_B(Im, L) (0xea000000 | (Im) | ((L) << 24))
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/* Branch and exchange (ARM state)
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* Rm: register holding branch target address
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*/
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#define ARMV4_5_BX(Rm) (0xe12fff10 | (Rm))
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/* Store data from coprocessor to consecutive memory
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* See Armv7-A arch doc section A8.6.187
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* P: 1=index mode (offset from Rn)
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* U: 1=add, 0=subtract Rn address with imm
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* D: Opcode D encoding
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* W: write back the offset start address to the Rn register
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* CP: Coprocessor number (4 bits)
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* CRd: Coprocessor source register (4 bits)
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* Rn: Base register for memory address (4 bits)
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* imm: Immediate value (0 - 1020, must be divisible by 4)
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*/
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#define ARMV4_5_STC(P, U, D, W, CP, CRd, Rn, imm) \
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(0xec000000 | ((P) << 24) | ((U) << 23) | ((D) << 22) | \
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((W) << 21) | ((Rn) << 16) | ((CRd) << 12) | ((CP) << 8) | ((imm)>>2))
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/* Loads data from consecutive memory to coprocessor
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* See Armv7-A arch doc section A8.6.51
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* P: 1=index mode (offset from Rn)
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* U: 1=add, 0=subtract Rn address with imm
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* D: Opcode D encoding
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* W: write back the offset start address to the Rn register
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* CP: Coprocessor number (4 bits)
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* CRd: Coprocessor dest register (4 bits)
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* Rn: Base register for memory address (4 bits)
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* imm: Immediate value (0 - 1020, must be divisible by 4)
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*/
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#define ARMV4_5_LDC(P, U, D, W, CP, CRd, Rn, imm) \
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(0xec100000 | ((P) << 24) | ((U) << 23) | ((D) << 22) | \
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((W) << 21) | ((Rn) << 16) | ((CRd) << 12) | ((CP) << 8) | ((imm) >> 2))
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/* Move to ARM register from coprocessor
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* CP: Coprocessor number
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* op1: Coprocessor opcode
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* Rd: destination register
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* CRn: first coprocessor operand
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* CRm: second coprocessor operand
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* op2: Second coprocessor opcode
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*/
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#define ARMV4_5_MRC(CP, op1, Rd, CRn, CRm, op2) \
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(0xee100010 | (CRm) | ((op2) << 5) | ((CP) << 8) \
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| ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21))
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/* Move to coprocessor from ARM register
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* CP: Coprocessor number
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* op1: Coprocessor opcode
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* Rd: destination register
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* CRn: first coprocessor operand
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* CRm: second coprocessor operand
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* op2: Second coprocessor opcode
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*/
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#define ARMV4_5_MCR(CP, op1, Rd, CRn, CRm, op2) \
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(0xee000010 | (CRm) | ((op2) << 5) | ((CP) << 8) \
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| ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21))
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/* Breakpoint instruction (ARMv5)
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* Im: 16-bit immediate
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*/
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#define ARMV5_BKPT(Im) (0xe1200070 | ((Im & 0xfff0) << 8) | (Im & 0xf))
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/* Thumb mode instructions
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*
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* NOTE: these 16-bit opcodes fill both halves of a word with the same
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* value. The reason for this is that when we need to execute Thumb
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* opcodes on ARM7/ARM9 cores (to switch to ARM state on debug entry),
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* we must shift 32 bits to the bus using scan chain 1 ... if we write
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* both halves, we don't need to track which half matters. On ARMv6 and
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* ARMv7 we don't execute Thumb instructions in debug mode; the ITR
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* register does not accept Thumb (or Thumb2) opcodes.
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*/
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/* Store register (Thumb mode)
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* Rd: source register
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* Rn: base register
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*/
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#define ARMV4_5_T_STR(Rd, Rn) \
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((0x6000 | (Rd) | ((Rn) << 3)) | \
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((0x6000 | (Rd) | ((Rn) << 3)) << 16))
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/* Load register (Thumb state)
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* Rd: destination register
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* Rn: base register
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*/
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#define ARMV4_5_T_LDR(Rd, Rn) \
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((0x6800 | ((Rn) << 3) | (Rd)) \
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| ((0x6800 | ((Rn) << 3) | (Rd)) << 16))
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/* Load multiple (Thumb state)
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* Rn: base register
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* List: for each bit in list: store register
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*/
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#define ARMV4_5_T_LDMIA(Rn, List) \
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((0xc800 | ((Rn) << 8) | (List)) \
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| ((0xc800 | ((Rn) << 8) | (List)) << 16))
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/* Load register with PC relative addressing
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* Rd: register to load
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*/
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#define ARMV4_5_T_LDR_PCREL(Rd) \
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((0x4800 | ((Rd) << 8)) \
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| ((0x4800 | ((Rd) << 8)) << 16))
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/* Move hi register (Thumb mode)
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* Rd: destination register
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* Rm: source register
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*/
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#define ARMV4_5_T_MOV(Rd, Rm) \
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((0x4600 | ((Rd) & 0x7) | (((Rd) & 0x8) << 4) | \
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(((Rm) & 0x7) << 3) | (((Rm) & 0x8) << 3)) \
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| ((0x4600 | ((Rd) & 0x7) | (((Rd) & 0x8) << 4) | \
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(((Rm) & 0x7) << 3) | (((Rm) & 0x8) << 3)) << 16))
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/* No operation (Thumb mode)
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* NOTE: this is "MOV r8, r8" ... Thumb2 adds two
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* architected NOPs, 16-bit and 32-bit.
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*/
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#define ARMV4_5_T_NOP (0x46c0 | (0x46c0 << 16))
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/* Move immediate to register (Thumb state)
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* Rd: destination register
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* Im: 8-bit immediate value
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*/
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#define ARMV4_5_T_MOV_IM(Rd, Im) \
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((0x2000 | ((Rd) << 8) | (Im)) \
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| ((0x2000 | ((Rd) << 8) | (Im)) << 16))
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/* Branch and Exchange
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* Rm: register containing branch target
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*/
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#define ARMV4_5_T_BX(Rm) \
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((0x4700 | ((Rm) << 3)) \
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| ((0x4700 | ((Rm) << 3)) << 16))
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/* Branch (Thumb state)
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* Imm: Branch target
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*/
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#define ARMV4_5_T_B(Imm) \
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((0xe000 | (Imm)) \
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| ((0xe000 | (Imm)) << 16))
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/* Breakpoint instruction (ARMv5) (Thumb state)
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* Im: 8-bit immediate
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*/
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#define ARMV5_T_BKPT(Im) \
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((0xbe00 | (Im)) \
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| ((0xbe00 | (Im)) << 16))
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/* Move to Register from Special Register
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* 32 bit Thumb2 instruction
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* Rd: destination register
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* SYSm: source special register
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*/
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#define ARM_T2_MRS(Rd, SYSm) \
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((0xF3EF) | ((0x8000 | (Rd << 8) | SYSm) << 16))
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/* Move from Register from Special Register
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* 32 bit Thumb2 instruction
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* Rd: source register
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* SYSm: destination special register
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*/
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#define ARM_T2_MSR(SYSm, Rn) \
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((0xF380 | (Rn << 8)) | ((0x8800 | SYSm) << 16))
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/* Change Processor State.
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* 16 bit Thumb2 instruction
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* Rd: source register
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* IF: A_FLAG and/or I_FLAG and/or F_FLAG
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*/
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#define A_FLAG 4
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#define I_FLAG 2
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#define F_FLAG 1
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#define ARM_T2_CPSID(IF) \
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((0xB660 | (1 << 8) | ((IF)&0x3)) \
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| ((0xB660 | (1 << 8) | ((IF)&0x3)) << 16))
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#define ARM_T2_CPSIE(IF) \
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((0xB660 | (0 << 8) | ((IF)&0x3)) \
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| ((0xB660 | (0 << 8) | ((IF)&0x3)) << 16))
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#endif /* __ARM_OPCODES_H */
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