106 lines
3.7 KiB
C
106 lines
3.7 KiB
C
/***************************************************************************
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* Copyright (C) 2010 by Oleksandr Tymoshenko <gonzo@bluezbox.com> *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, write to the *
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* Free Software Foundation, Inc., *
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
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***************************************************************************/
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#ifndef AVR32_JTAG
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#define AVR32_JTAG
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#define AVR32NUMCOREREGS 17
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/* tap instructions */
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#define AVR32_INST_IDCODE 0x01
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#define AVR32_INST_NEXUS_ACCESS 0x10
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#define AVR32_INST_MW_ACCESS 0x11
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#define AVR32_INST_MB_ACCESS 0x12
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#define SLAVE_OCD 0x01
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#define SLAVE_HSB_CACHED 0x04
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#define SLAVE_HSB_UNCACHED 0x05
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/*
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* Registers
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*/
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#define AVR32_OCDREG_DID 0x00
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#define AVR32_OCDREG_DC 0x02
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#define OCDREG_DC_SS (1 << 8)
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#define OCDREG_DC_DBR (1 << 12)
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#define OCDREG_DC_DBE (1 << 13)
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#define OCDREG_DC_SQA (1 << 22)
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#define OCDREG_DC_RES (1 << 30)
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#define OCDREG_DC_ABORT (1 << 31)
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#define AVR32_OCDREG_DS 0x04
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#define OCDREG_DS_SSS (1 << 0)
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#define OCDREG_DS_SWB (1 << 1)
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#define OCDREG_DS_HWB (1 << 2)
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#define OCDREG_DS_STP (1 << 4)
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#define OCDREG_DS_DBS (1 << 5)
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#define OCDREG_DS_BP_SHIFT 8
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#define OCDREG_DS_BP_MASK 0xff
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#define OCDREG_DS_INC (1 << 24)
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#define OCDREG_DS_BOZ (1 << 25)
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#define OCDREG_DS_DBA (1 << 26)
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#define OCDREG_DS_EXB (1 << 27)
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#define OCDREG_DS_NTBF (1 << 28)
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#define AVR32_OCDREG_DINST 0x41
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#define AVR32_OCDREG_DPC 0x42
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#define AVR32_OCDREG_DCCPU 0x44
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#define AVR32_OCDREG_DCEMU 0x45
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#define AVR32_OCDREG_DCSR 0x46
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#define OCDREG_DCSR_CPUD (1 << 0)
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#define OCDREG_DCSR_EMUD (1 << 1)
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/*
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* Direction bit
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*/
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#define MODE_WRITE 0x00
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#define MODE_READ 0x01
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/*
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* Some instructions
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*/
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#define RETD 0xd703d623
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#define MTDR(dreg, reg) (0xe7b00044 | ((reg) << 16) | dreg)
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#define MFDR(reg, dreg) (0xe5b00044 | ((reg) << 16) | dreg)
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#define MTSR(sysreg, reg) (0xe3b00002 | ((reg) << 16) | sysreg)
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#define MFSR(reg, sysreg) (0xe1b00002 | ((reg) << 16) | sysreg)
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struct avr32_jtag {
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struct jtag_tap *tap;
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uint32_t dpc; /* Debug PC value */
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};
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int avr32_jtag_nexus_read(struct avr32_jtag *jtag_info,
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uint32_t addr, uint32_t *value);
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int avr32_jtag_nexus_write(struct avr32_jtag *jtag_info,
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uint32_t addr, uint32_t value);
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int avr32_jtag_mwa_read(struct avr32_jtag *jtag_info, int slave,
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uint32_t addr, uint32_t *value);
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int avr32_jtag_mwa_write(struct avr32_jtag *jtag_info, int slave,
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uint32_t addr, uint32_t value);
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int avr32_ocd_setbits(struct avr32_jtag *jtag, int reg, uint32_t bits);
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int avr32_ocd_clearbits(struct avr32_jtag *jtag, int reg, uint32_t bits);
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int avr32_jtag_exec(struct avr32_jtag *jtag_info, uint32_t inst);
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#endif /* AVR32_JTAG */
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