8e5eaac529
Derived from tcl/interface/digilent-hs1.cfg. JTAG-HS3 has an open drain buffer on pin 14 for SRST to work with PS_SRST_B on Xilinx Zynq SoC. Change-Id: I1e9e72d0511528a61207e318aff937ae9fad5bf9 Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-on: http://openocd.zylin.com/2728 Tested-by: jenkins Reviewed-by: Robert Jordens <jordens@gmail.com> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
14 lines
290 B
INI
14 lines
290 B
INI
#
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# Digilent JTAG-HS3
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#
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interface ftdi
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ftdi_vid_pid 0x0403 0x6014
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ftdi_device_desc "Digilent USB Device"
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# From Digilent support:
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# The SRST pin is [...] 0x20 and 0x10 is the /OE (active low output enable)
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ftdi_layout_init 0x2088 0x308b
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ftdi_layout_signal nSRST -data 0x2000 -noe 0x1000
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