160 lines
6.6 KiB
INI
160 lines
6.6 KiB
INI
# Main file for NXP LPC1xxx/LPC40xx series Cortex-M0/0+/3/4F parts
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#
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# !!!!!!
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#
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# This file should not be included directly, rather by the lpc11xx.cfg,
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# lpc13xx.cfg, lpc17xx.cfg, etc. which set the needed variables to the
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# appropriate values.
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#
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# !!!!!!
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# LPC8xx chips support only SWD transport.
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# LPC11xx chips support only SWD transport.
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# LPC12xx chips support only SWD transport.
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# LPC11Uxx chips support only SWD transports.
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# LPC13xx chips support only SWD transports.
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# LPC17xx chips support both JTAG and SWD transports.
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# LPC40xx chips support both JTAG and SWD transports.
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# Adapt based on what transport is active.
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source [find target/swj-dp.tcl]
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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error "CHIPNAME not set. Please do not include lpc1xxx.cfg directly, but the specific chip configuration file (lpc11xx.cfg, lpc13xx.cfg, lpc17xx.cfg, etc)."
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}
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if { [info exists CHIPSERIES] } {
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# Validate chip series is supported
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if { $CHIPSERIES != "lpc800" && $CHIPSERIES != "lpc1100" && $CHIPSERIES != "lpc1200" && $CHIPSERIES != "lpc1300" && $CHIPSERIES != "lpc1700" && $CHIPSERIES != "lpc4000" } {
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error "Unsupported LPC1xxx chip series specified."
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}
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set _CHIPSERIES $CHIPSERIES
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} else {
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error "CHIPSERIES not set. Please do not include lpc1xxx.cfg directly, but the specific chip configuration file (lpc11xx.cfg, lpc13xx.cfg, lpc17xx.cfg, etc)."
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}
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# After reset, the chip is clocked by an internal RC oscillator.
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# When board-specific code (reset-init handler or device firmware)
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# configures another oscillator and/or PLL0, set CCLK to match; if
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# you don't, then flash erase and write operations may misbehave.
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# (The ROM code doing those updates cares about core clock speed...)
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# CCLK is the core clock frequency in KHz
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if { [info exists CCLK] } {
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# Allow user override
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set _CCLK $CCLK
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} else {
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# LPC8xx/LPC11xx/LPC12xx/LPC13xx use a 12MHz one, LPC17xx uses a 4MHz one(except for LPC177x/8x,LPC407x/8x)
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if { $_CHIPSERIES == "lpc800" || $_CHIPSERIES == "lpc1100" || $_CHIPSERIES == "lpc1200" || $_CHIPSERIES == "lpc1300" } {
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set _CCLK 12000
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} elseif { $_CHIPSERIES == "lpc1700" || $_CHIPSERIES == "lpc4000" } {
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set _CCLK 4000
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}
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}
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if { [info exists CPUTAPID] } {
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# Allow user override
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set _CPUTAPID $CPUTAPID
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} else {
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# LPC8xx/LPC11xx/LPC12xx use a Cortex-M0/M0+ core, LPC13xx/LPC17xx use a Cortex-M3 core, LPC40xx use a Cortex-M4F core.
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if { $_CHIPSERIES == "lpc800" || $_CHIPSERIES == "lpc1100" || $_CHIPSERIES == "lpc1200" } {
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set _CPUTAPID 0x0bb11477
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} elseif { $_CHIPSERIES == "lpc1300" || $_CHIPSERIES == "lpc1700" || $_CHIPSERIES == "lpc4000" } {
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if { [using_jtag] } {
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set _CPUTAPID 0x4ba00477
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} {
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set _CPUTAPID 0x2ba01477
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}
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}
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}
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if { [info exists WORKAREASIZE] } {
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set _WORKAREASIZE $WORKAREASIZE
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} else {
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error "WORKAREASIZE is not set. The $CHIPNAME part is available in several Flash and RAM size configurations. Please set WORKAREASIZE."
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}
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swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME
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# The LPC11xx devices have 2/4/8kB of SRAM in the ARMv7-M "Code" area (at 0x10000000)
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# The LPC12xx devices have 4/8kB of SRAM in the ARMv7-M "Code" area (at 0x10000000)
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# The LPC11Uxx devices have 4/6/8kB of SRAM in the ARMv7-M "Code" area (at 0x10000000)
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# The LPC13xx devices have 4/8kB of SRAM in the ARMv7-M "Code" area (at 0x10000000)
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# The LPC17xx devices have 8/16/32/64kB of SRAM in the ARMv7-M "Code" area (at 0x10000000)
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# The LPC40xx devices have 16/32/64kB of SRAM in the ARMv7-ME "Code" area (at 0x10000000)
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$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size $_WORKAREASIZE
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# The LPC11xx devies have 8/16/24/32/48/56/64kB of flash memory (at 0x00000000)
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# The LPC12xx devies have 32/48/64/80/96/128kB of flash memory (at 0x00000000)
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# The LPC11Uxx devies have 16/24/32/40/48/64/96/128kB of flash memory (at 0x00000000)
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# The LPC13xx devies have 8/16/32kB of flash memory (at 0x00000000)
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# The LPC17xx devies have 32/64/128/256/512kB of flash memory (at 0x00000000)
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# The LPC40xx devies have 64/128/256/512kB of flash memory (at 0x00000000)
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#
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# All are compatible with the "lpc1700" variant of the LPC2000 flash driver
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# (same cmd51 destination boundary alignment, and all three support 256 byte
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# transfers).
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#
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# flash bank <name> lpc2000 <base> <size> 0 0 <target#> <variant> <clock> [calc checksum]
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set _FLASHNAME $_CHIPNAME.flash
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flash bank $_FLASHNAME lpc2000 0x0 0 0 0 $_TARGETNAME \
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auto $_CCLK calc_checksum
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if { $_CHIPSERIES == "lpc800" || $_CHIPSERIES == "lpc1100" || $_CHIPSERIES == "lpc1200" || $_CHIPSERIES == "lpc1300" } {
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# Do not remap 0x0000-0x0200 to anything but the flash (i.e. select
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# "User Flash Mode" where interrupt vectors are _not_ remapped,
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# and reside in flash instead).
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#
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# Table 8. System memory remap register (SYSMEMREMAP, address 0x4004 8000) bit description
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# Bit Symbol Value Description
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# 1:0 MAP System memory remap
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# 0x0 Boot Loader Mode. Interrupt vectors are re-mapped to Boot ROM.
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# 0x1 User RAM Mode. Interrupt vectors are re-mapped to Static RAM.
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# 0x2 User Flash Mode. Interrupt vectors are not re-mapped and reside in Flash.
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# 31:2 - - Reserved.
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$_TARGETNAME configure -event reset-init {
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mww 0x40048000 0x02
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}
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} elseif { $_CHIPSERIES == "lpc1700" || $_CHIPSERIES == "lpc4000" } {
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# Do not remap 0x0000-0x0020 to anything but the flash (i.e. select
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# "User Flash Mode" where interrupt vectors are _not_ remapped,
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# and reside in flash instead).
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#
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# See Table 612. Memory Mapping Control register (MEMMAP - 0x400F C040) bit description
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# Bit Symbol Value Description Reset
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# value
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# 0 MAP Memory map control. 0
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# 0 Boot mode. A portion of the Boot ROM is mapped to address 0.
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# 1 User mode. The on-chip Flash memory is mapped to address 0.
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# 31:1 - Reserved. The value read from a reserved bit is not defined. NA
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#
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# http://ics.nxp.com/support/documents/microcontrollers/?scope=LPC1768&type=user
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$_TARGETNAME configure -event reset-init {
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mww 0x400FC040 0x01
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}
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}
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# Run with *real slow* clock by default since the
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# boot rom could have been playing with the PLL, so
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# we have no idea what clock the target is running at.
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adapter_khz 10
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# delays on reset lines
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adapter_nsrst_delay 200
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if {[using_jtag]} {
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jtag_ntrst_delay 200
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}
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# LPC8xx (Cortex-M0+ core) support SYSRESETREQ
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# LPC11xx/LPC12xx (Cortex-M0 core) support SYSRESETREQ
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# LPC13xx/LPC17xx (Cortex-M3 core) support SYSRESETREQ
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# LPC40xx (Cortex-M4F core) support SYSRESETREQ
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if {![using_hla]} {
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# if srst is not fitted use SYSRESETREQ to
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# perform a soft reset
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cortex_m reset_config sysresetreq
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}
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