0c8ec7c826
It's Cortex-Xn, not Cortex Xn or cortex xn or cortex-xn or CORTEX-Xn or CortexXn. Further it's Cortex-M0+, not M0plus. Cf. http://www.arm.com/products/processors/index.php Consistently write it the official way, so that it stops propagating. Originally spotted in the documentation, it mainly affects code comments but also Atmel SAM3/SAM4/SAMV, NiietCM4 and SiM3x flash driver output. Found via: git grep -i "Cortex " git grep -i "Cortex-" | grep -v "Cortex-" | grep -v ".cpu" git grep -i "CortexM" Change-Id: Ic7b6ca85253e027f6f0f751c628d1a2a391fe914 Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-on: http://openocd.zylin.com/3483 Tested-by: jenkins Reviewed-by: Marc Schink <openocd-dev@marcschink.de> Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
60 lines
1.7 KiB
INI
60 lines
1.7 KiB
INI
# Freescale i.MX6 series single/dual/quad core processor
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME imx6
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}
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# CoreSight Debug Access Port
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if { [info exists DAP_TAPID] } {
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set _DAP_TAPID $DAP_TAPID
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} else {
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set _DAP_TAPID 0x4ba00477
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}
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jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x01 -irmask 0x0f \
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-expected-id $_DAP_TAPID
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# SDMA / no IDCODE
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jtag newtap $_CHIPNAME sdma -irlen 4 -ircapture 0x00 -irmask 0x0f
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# System JTAG Controller
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if { [info exists SJC_TAPID] } {
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set _SJC_TAPID $SJC_TAPID
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} else {
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set _SJC_TAPID 0x0191c01d
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}
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set _SJC_TAPID2 0x2191c01d
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set _SJC_TAPID3 0x2191e01d
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set _SJC_TAPID4 0x1191c01d
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jtag newtap $_CHIPNAME sjc -irlen 5 -ircapture 0x01 -irmask 0x1f \
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-expected-id $_SJC_TAPID -expected-id $_SJC_TAPID2 \
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-expected-id $_SJC_TAPID3 -expected-id $_SJC_TAPID4
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# GDB target: Cortex-A9, using DAP, configuring only one core
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# Base addresses of cores:
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# core 0 - 0x82150000
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# core 1 - 0x82152000
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# core 2 - 0x82154000
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# core 3 - 0x82156000
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set _TARGETNAME $_CHIPNAME.cpu.0
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target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap \
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-coreid 0 -dbgbase 0x82150000
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# some TCK cycles are required to activate the DEBUG power domain
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jtag configure $_CHIPNAME.sjc -event post-reset "runtest 100"
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proc imx6_dbginit {target} {
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# General Cortex-A8/A9 debug initialisation
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cortex_a dbginit
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}
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# Slow speed to be sure it will work
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adapter_khz 1000
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$_TARGETNAME configure -event reset-start { adapter_khz 1000 }
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$_TARGETNAME configure -event reset-assert-post "imx6_dbginit $_TARGETNAME"
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$_TARGETNAME configure -event gdb-attach { halt }
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