openocd/tcl/target/imx6.cfg
Andreas Färber 0c8ec7c826 Fix spelling of ARM Cortex
It's Cortex-Xn, not Cortex Xn or cortex xn or cortex-xn or CORTEX-Xn
or CortexXn. Further it's Cortex-M0+, not M0plus.

Cf. http://www.arm.com/products/processors/index.php

Consistently write it the official way, so that it stops propagating.
Originally spotted in the documentation, it mainly affects code comments
but also Atmel SAM3/SAM4/SAMV, NiietCM4 and SiM3x flash driver output.

Found via:

  git grep -i "Cortex "
  git grep -i "Cortex-" | grep -v "Cortex-" | grep -v ".cpu"
  git grep -i "CortexM"

Change-Id: Ic7b6ca85253e027f6f0f751c628d1a2a391fe914
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/3483
Tested-by: jenkins
Reviewed-by: Marc Schink <openocd-dev@marcschink.de>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2016-05-20 21:38:03 +01:00

60 lines
1.7 KiB
INI

# Freescale i.MX6 series single/dual/quad core processor
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME imx6
}
# CoreSight Debug Access Port
if { [info exists DAP_TAPID] } {
set _DAP_TAPID $DAP_TAPID
} else {
set _DAP_TAPID 0x4ba00477
}
jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x01 -irmask 0x0f \
-expected-id $_DAP_TAPID
# SDMA / no IDCODE
jtag newtap $_CHIPNAME sdma -irlen 4 -ircapture 0x00 -irmask 0x0f
# System JTAG Controller
if { [info exists SJC_TAPID] } {
set _SJC_TAPID $SJC_TAPID
} else {
set _SJC_TAPID 0x0191c01d
}
set _SJC_TAPID2 0x2191c01d
set _SJC_TAPID3 0x2191e01d
set _SJC_TAPID4 0x1191c01d
jtag newtap $_CHIPNAME sjc -irlen 5 -ircapture 0x01 -irmask 0x1f \
-expected-id $_SJC_TAPID -expected-id $_SJC_TAPID2 \
-expected-id $_SJC_TAPID3 -expected-id $_SJC_TAPID4
# GDB target: Cortex-A9, using DAP, configuring only one core
# Base addresses of cores:
# core 0 - 0x82150000
# core 1 - 0x82152000
# core 2 - 0x82154000
# core 3 - 0x82156000
set _TARGETNAME $_CHIPNAME.cpu.0
target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap \
-coreid 0 -dbgbase 0x82150000
# some TCK cycles are required to activate the DEBUG power domain
jtag configure $_CHIPNAME.sjc -event post-reset "runtest 100"
proc imx6_dbginit {target} {
# General Cortex-A8/A9 debug initialisation
cortex_a dbginit
}
# Slow speed to be sure it will work
adapter_khz 1000
$_TARGETNAME configure -event reset-start { adapter_khz 1000 }
$_TARGETNAME configure -event reset-assert-post "imx6_dbginit $_TARGETNAME"
$_TARGETNAME configure -event gdb-attach { halt }