67 lines
1.9 KiB
INI
67 lines
1.9 KiB
INI
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME lpc2900
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}
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if { [info exists CPUTAPID] } {
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set _CPUTAPID $CPUTAPID
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} else {
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set _CPUTAPID 0x0596802B
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}
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if { [info exists HAS_ETB] } {
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} else {
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# Set default (no ETB).
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# Show a warning, because this should have been configured explicitely.
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set HAS_ETB 0
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# TODO: warning?
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}
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if { [info exists ETBTAPID] } {
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set _ETBTAPID $ETBTAPID
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} else {
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set _ETBTAPID 0x1B900F0F
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}
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# TRST and SRST both exist, and can be controlled independently
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reset_config trst_and_srst separate
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# Define the _TARGETNAME
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set _TARGETNAME $_CHIPNAME.cpu
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# Include the ETB tap controller if asked for.
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# Has to be done manually for newer devices (not an "old" LPC2917/2919).
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if { $HAS_ETB == 1 } {
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# Clear the HAS_ETB flag. Must be set again for a new tap in the chain.
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set HAS_ETB 0
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# Add the ETB tap controller and the ARM9 core debug tap
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jtag newtap $_CHIPNAME etb -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_ETBTAPID
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jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
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# Create the ".cpu" target
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target create $_TARGETNAME arm966e -endian little -chain-position $_TARGETNAME
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# Configure ETM and ETB
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etm config $_TARGETNAME 8 normal full etb
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etb config $_TARGETNAME $_CHIPNAME.etb
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} else {
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# Add the ARM9 core debug tap
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jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
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# Create the ".cpu" target
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target create $_TARGETNAME arm966e -endian little -chain-position $_TARGETNAME
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}
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arm7_9 dbgrq enable
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arm7_9 dcc_downloads enable
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# Flash bank configuration:
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# Flash: flash bank lpc2900 0 0 0 0 <target#> <flash clock (CLK_SYS_FMC) in kHz>
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# Flash base address, total flash size, and number of sectors are all configured automatically.
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set _FLASHNAME $_CHIPNAME.flash
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flash bank $_FLASHNAME lpc2900 0 0 0 0 $_TARGETNAME $FLASH_CLOCK
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