d25355473d
Many FPGA board speak JTAG and have a SPI flash for their bitstream attached to them. The SPI flash is programmed by first uploading a proxy bitstream to the FPGA that connects the JTAG interface to the SPI interface if the IR contains a certain USER instruction. Then the SPI flash can be erase, written, read directly through the JTAG DR. The JTAG and SPI signaling is compatible. Such a proxy bitstream only needs to connect TDO-MISO, TDI-MOSI, TCK-CLK, and the activate the chip select when the IR contains the special instruction and the JTAG state machine is in the DR-SHIFT state. Change-Id: Ibc21d793a83b36fa37e2704966aa5c837c4dd0d2 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/2844 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
44 lines
934 B
INI
44 lines
934 B
INI
set _USER1 0x02
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if { [info exists JTAGSPI_IR] } {
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set _JTAGSPI_IR $JTAGSPI_IR
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} else {
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set _JTAGSPI_IR $_USER1
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}
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if { [info exists DR_LENGTH] } {
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set _DR_LENGTH $DR_LENGTH
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} else {
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set _DR_LENGTH 1
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}
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if { [info exists TARGETNAME] } {
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set _TARGETNAME $TARGETNAME
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} else {
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set _TARGETNAME $_CHIPNAME.proxy
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}
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if { [info exists FLASHNAME] } {
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set _FLASHNAME $FLASHNAME
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} else {
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set _FLASHNAME $_CHIPNAME.spi
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}
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target create $_TARGETNAME testee -chain-position $_CHIPNAME.tap
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flash bank $_FLASHNAME jtagspi 0 0 0 0 $_TARGETNAME $_JTAGSPI_IR $_DR_LENGTH
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proc jtagspi_init {chain_id proxy_bit} {
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# load proxy bitstream $proxy_bit and probe spi flash
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global _FLASHNAME
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pld load $chain_id $proxy_bit
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reset halt
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flash probe $_FLASHNAME
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}
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proc jtagspi_program {bin addr} {
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# write and verify binary file $bin at offset $addr
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global _FLASHNAME
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flash write_image erase $bin $addr
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flash verify_bank $_FLASHNAME $bin $addr
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}
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