0c8ec7c826
It's Cortex-Xn, not Cortex Xn or cortex xn or cortex-xn or CORTEX-Xn or CortexXn. Further it's Cortex-M0+, not M0plus. Cf. http://www.arm.com/products/processors/index.php Consistently write it the official way, so that it stops propagating. Originally spotted in the documentation, it mainly affects code comments but also Atmel SAM3/SAM4/SAMV, NiietCM4 and SiM3x flash driver output. Found via: git grep -i "Cortex " git grep -i "Cortex-" | grep -v "Cortex-" | grep -v ".cpu" git grep -i "CortexM" Change-Id: Ic7b6ca85253e027f6f0f751c628d1a2a391fe914 Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-on: http://openocd.zylin.com/3483 Tested-by: jenkins Reviewed-by: Marc Schink <openocd-dev@marcschink.de> Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
28 lines
1020 B
INI
28 lines
1020 B
INI
# script for ATMEL sam4l, a Cortex-M4 chip
|
|
#
|
|
|
|
source [find target/at91sam4XXX.cfg]
|
|
|
|
set _FLASHNAME $_CHIPNAME.flash
|
|
flash bank $_FLASHNAME at91sam4l 0x00000000 0 1 1 $_TARGETNAME
|
|
|
|
# SAM4L SMAP will hold the CPU in reset if TCK is low when RESET_N
|
|
# deasserts (see datasheet 42023E-SAM-07/2013 sec 8.11.3).
|
|
#
|
|
# smap_reset_deassert configures whether we want to run or halt out of reset,
|
|
# then instruct the SMAP to let us out of reset.
|
|
$_TARGETNAME configure -event reset-deassert-post "at91sam4l smap_reset_deassert"
|
|
|
|
# SRST (wired to RESET_N) resets debug circuitry
|
|
# srst_pulls_trst is not configured here to avoid an error raised in reset halt
|
|
reset_config srst_gates_jtag
|
|
|
|
# SAM4L starts from POR with SYSCLK set to 115kHz RCSYS, needs slow JTAG speed.
|
|
# Datasheet does not specify SYSCLK to JTAG/SWD clock ratio.
|
|
# Usually used SYSCLK/6 is hell slow, testing shows that debugging can work @ SYSCLK/2
|
|
# but your mileage may vary.
|
|
adapter_khz 50
|
|
|
|
# System RC oscillator RCSYS starts in 3 cycles
|
|
adapter_nsrst_delay 0
|