66 lines
2.6 KiB
C
66 lines
2.6 KiB
C
/***************************************************************************
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* ESP32-S3 target for OpenOCD *
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* Copyright (C) 2020 Espressif Systems Ltd. *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program. If not, see <http://www.gnu.org/licenses/>. *
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***************************************************************************/
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#ifndef OPENOCD_TARGET_ESP32S3_H
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#define OPENOCD_TARGET_ESP32S3_H
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#include <target/xtensa/xtensa_regs.h>
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#define ESP32_S3_DROM_LOW 0x3C000000
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#define ESP32_S3_DROM_HIGH 0x3D000000
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#define ESP32_S3_IROM_LOW 0x42000000
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#define ESP32_S3_IROM_HIGH 0x44000000
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/*Number of registers returned directly by the G command
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*Corresponds to the amount of regs listed in regformats/reg-xtensa.dat in the gdb source */
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#define ESP32_S3_NUM_REGS_G_COMMAND 128
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enum esp32s3_reg_id {
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/* chip specific registers that extend ISA go after ISA-defined ones */
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ESP32_S3_REG_IDX_GPIOOUT = XT_NUM_REGS,
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ESP32_S3_REG_IDX_ACCX_0,
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ESP32_S3_REG_IDX_ACCX_1,
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ESP32_S3_REG_IDX_QACC_H_0,
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ESP32_S3_REG_IDX_QACC_H_1,
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ESP32_S3_REG_IDX_QACC_H_2,
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ESP32_S3_REG_IDX_QACC_H_3,
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ESP32_S3_REG_IDX_QACC_H_4,
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ESP32_S3_REG_IDX_QACC_L_0,
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ESP32_S3_REG_IDX_QACC_L_1,
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ESP32_S3_REG_IDX_QACC_L_2,
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ESP32_S3_REG_IDX_QACC_L_3,
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ESP32_S3_REG_IDX_QACC_L_4,
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ESP32_S3_REG_IDX_SAR_BYTE,
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ESP32_S3_REG_IDX_FFT_BIT_WIDTH,
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ESP32_S3_REG_IDX_UA_STATE_0,
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ESP32_S3_REG_IDX_UA_STATE_1,
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ESP32_S3_REG_IDX_UA_STATE_2,
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ESP32_S3_REG_IDX_UA_STATE_3,
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ESP32_S3_REG_IDX_Q0,
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ESP32_S3_REG_IDX_Q1,
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ESP32_S3_REG_IDX_Q2,
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ESP32_S3_REG_IDX_Q3,
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ESP32_S3_REG_IDX_Q4,
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ESP32_S3_REG_IDX_Q5,
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ESP32_S3_REG_IDX_Q6,
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ESP32_S3_REG_IDX_Q7,
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ESP32_S3_NUM_REGS,
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};
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#endif /* OPENOCD_TARGET_ESP32S3_H */
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