20d18d415d
STM32F7xx devices need faster clock for flash programming
over JTAG transport. Using reset default 16 MHz clock
resulted in lot of DAP WAITs and substantial decrease
of flashing performance.
Adapted to the restructured dap support
(see 2231da8ec4).
Change-Id: Ida6915331dd924c9c0d08822fd94c04ad408cdc5
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4464
Tested-by: jenkins
Reviewed-by: Christopher Head <chead@zaber.com>
109 lines
2.9 KiB
INI
Executable File
109 lines
2.9 KiB
INI
Executable File
# script for stm32f7x family
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#
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# stm32f7 devices support both JTAG and SWD transports.
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#
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source [find target/swj-dp.tcl]
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source [find mem_helper.tcl]
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME stm32f7x
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}
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set _ENDIAN little
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# Work-area is a space in RAM used for flash programming
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# By default use 128kB
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if { [info exists WORKAREASIZE] } {
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set _WORKAREASIZE $WORKAREASIZE
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} else {
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set _WORKAREASIZE 0x20000
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}
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#jtag scan chain
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if { [info exists CPUTAPID] } {
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set _CPUTAPID $CPUTAPID
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} else {
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if { [using_jtag] } {
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# See STM Document RM0385
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# Section 40.6.3 - corresponds to Cortex-M7 with FPU r0p0
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set _CPUTAPID 0x5ba00477
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} {
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set _CPUTAPID 0x5ba02477
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}
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}
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swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
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dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
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if {[using_jtag]} {
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jtag newtap $_CHIPNAME bs -irlen 5
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}
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
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$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
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set _FLASHNAME $_CHIPNAME.flash
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flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME
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# adapter speed should be <= F_CPU/6. F_CPU after reset is 16MHz, so use F_JTAG = 2MHz
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adapter_khz 2000
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adapter_nsrst_delay 100
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if {[using_jtag]} {
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jtag_ntrst_delay 100
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}
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# use hardware reset, connect under reset
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reset_config srst_only srst_nogate
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if {![using_hla]} {
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# if srst is not fitted use SYSRESETREQ to
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# perform a soft reset
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cortex_m reset_config sysresetreq
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}
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$_TARGETNAME configure -event examine-end {
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# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
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mmw 0xE0042004 0x00000007 0
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# Stop watchdog counters during halt
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# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
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mmw 0xE0042008 0x00001800 0
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}
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$_TARGETNAME configure -event trace-config {
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# Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
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# change this value accordingly to configure trace pins
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# assignment
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mmw 0xE0042004 0x00000020 0
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}
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$_TARGETNAME configure -event reset-init {
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# Configure PLL to boost clock to HSI x 10 (160 MHz)
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mww 0x40023804 0x08002808 ;# RCC_PLLCFGR 16 Mhz /10 (M) * 128 (N) /2(P)
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mww 0x40023C00 0x00000107 ;# FLASH_ACR = PRFTBE | 7(Latency)
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mmw 0x40023800 0x01000000 0 ;# RCC_CR |= PLLON
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sleep 10 ;# Wait for PLL to lock
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mww 0x40023808 0x00009400 ;# RCC_CFGR_PPRE1 = 5(div 4), PPRE2 = 4(div 2)
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mmw 0x40023808 0x00000002 0 ;# RCC_CFGR |= RCC_CFGR_SW_PLL
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# Boost SWD frequency
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# Do not boost JTAG frequency and slow down JTAG memory access or flash write algo
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# suffers from DAP WAITs
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if {[using_jtag]} {
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[[target current] cget -dap] memaccess 16
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} {
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adapter_khz 8000
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}
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}
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$_TARGETNAME configure -event reset-start {
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# Reduce speed since CPU speed will slow down to 16MHz with the reset
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adapter_khz 2000
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}
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