- make ep93xx and at91rm9200 bitbang JTAG interfaces dependant on ARM host (thanks to Vincent Palatin) - various whitespace fixes - removed various warnings - add support for Debian GNU/kFreeBSD (thanks to Uwe Hermann) - fix OpenOCD compilation for various platforms (thanks to Uwe Hermann and Vincent Palatin) - switched order of JTAG chain examination and validation (examine first, then multiple validation tries even if examination failed) - added target_request subsystem to handle requests from the target (debug messages and tracepoints implemented, future enhancements might include semihosting, all ARM7/9 only for now) - added support for GDB vFlashXXX packets (thanks to Pavel Chromy) - added support for receiving data via ARM7/9 DCC - reworked flash writing. the 'flash write' command is now deprecated and replaced by 'flash write_binary' (old syntax and behaviour) and 'flash write_image' (write image files (bin, hex, elf, s19) to a target). - added support for AMD/ST/SST 29F400B non-cfi flashes git-svn-id: svn://svn.berlios.de/openocd/trunk@190 b42882b7-edfa-0310-969c-e2dbd0fdcd60
97 lines
2.8 KiB
C
97 lines
2.8 KiB
C
/***************************************************************************
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* Copyright (C) 2006 by Magnus Lundin *
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* lundinªmlu.mine.nu *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, write to the *
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* Free Software Foundation, Inc., *
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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***************************************************************************/
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#ifndef STELLARIS_FLASH_H
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#define STELLARIS_FLASH_H
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#include "flash.h"
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#include "target.h"
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typedef struct stellaris_flash_bank_s
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{
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/* chip id register */
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u32 did0;
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u32 did1;
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u32 dc0;
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u32 dc1;
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char * target_name;
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u32 sramsiz;
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u32 flshsz;
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/* flash geometry */
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u32 num_pages;
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u32 pagesize;
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u32 pages_in_lockregion;
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/* nv memory bits */
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u16 num_lockbits;
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u32 lockbits;
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/* main clock status */
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u32 rcc;
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u8 mck_valid;
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u32 mck_freq;
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} stellaris_flash_bank_t;
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/* STELLARIS control registers */
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#define SCB_BASE 0x400FE000
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#define DID0 0x000
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#define DID1 0x004
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#define DC0 0x008
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#define DC1 0x010
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#define DC2 0x014
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#define DC3 0x018
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#define DC4 0x01C
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#define RIS 0x050
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#define RCC 0x060
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#define PLLCFG 0x064
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#define FMPRE 0x130
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#define FMPPE 0x134
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#define USECRL 0x140
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#define FLASH_CONTROL_BASE 0x400FD000
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#define FLASH_FMA (FLASH_CONTROL_BASE|0x000)
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#define FLASH_FMD (FLASH_CONTROL_BASE|0x004)
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#define FLASH_FMC (FLASH_CONTROL_BASE|0x008)
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#define FLASH_CRIS (FLASH_CONTROL_BASE|0x00C)
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#define FLASH_CIM (FLASH_CONTROL_BASE|0x010)
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#define FLASH_MISC (FLASH_CONTROL_BASE|0x014)
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#define AMISC 1
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#define PMISC 2
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#define AMASK 1
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#define PMASK 2
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/* Flash Controller Command bits */
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#define FMC_WRKEY (0xA442<<16)
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#define FMC_COMT (1<<3)
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#define FMC_MERASE (1<<2)
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#define FMC_ERASE (1<<1)
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#define FMC_WRITE (1<<0)
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/* STELLARIS constants */
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#endif /* STELLARIS_H */
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