2279c23cde
Micromips is 16bit oriented, branch and jumps are 16 bit based. The upper half 16bits of a 32bit instruction with the major opcode, must go first in the instruction stream, hence the SWAP16 macro and swap16 array function, needed if the code is written as 32 bit word in little endian cores. Endianess info added to ejtag_iinfo. Pointer to ejtag_info and isa field added to pracc context. MIPS32 code are renamed to MIPS32_ISA_... To select the isa, the new code has an additional isa parameter (1 for micromips, 0 for mips32). In JR instruction the isa bit must be set to execute micromips code. The suffix u is added to the OP codes to avoid signed/unsigned comparison errors and to make sure the right shift is performed logically. The isa in debug mode is updated in the poll function. Code for miniprograms, in kernel mode, need to be converted. CFI code only for mips32. Change-Id: I79a8b637d49b0e2d92b6dd5eb5aa8aa0520bf938 Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/4032 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
460 lines
13 KiB
C
460 lines
13 KiB
C
/***************************************************************************
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* Copyright (C) 2008 by Spencer Oliver *
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* spen@spen-soft.co.uk *
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* *
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* Copyright (C) 2008 by David T.L. Wong *
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* *
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* Copyright (C) 2009 by David N. Claffey <dnclaffey@gmail.com> *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program. If not, see <http://www.gnu.org/licenses/>. *
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***************************************************************************/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include "mips32.h"
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#include "mips_ejtag.h"
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#include "mips32_dmaacc.h"
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void mips_ejtag_set_instr(struct mips_ejtag *ejtag_info, uint32_t new_instr)
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{
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assert(ejtag_info->tap != NULL);
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struct jtag_tap *tap = ejtag_info->tap;
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if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != new_instr) {
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struct scan_field field;
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field.num_bits = tap->ir_length;
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uint8_t t[4];
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field.out_value = t;
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buf_set_u32(t, 0, field.num_bits, new_instr);
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field.in_value = NULL;
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jtag_add_ir_scan(tap, &field, TAP_IDLE);
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}
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}
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int mips_ejtag_get_idcode(struct mips_ejtag *ejtag_info, uint32_t *idcode)
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{
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struct scan_field field;
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uint8_t r[4];
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_IDCODE);
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field.num_bits = 32;
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field.out_value = NULL;
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field.in_value = r;
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jtag_add_dr_scan(ejtag_info->tap, 1, &field, TAP_IDLE);
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int retval;
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retval = jtag_execute_queue();
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if (retval != ERROR_OK) {
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LOG_ERROR("register read failed");
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return retval;
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}
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*idcode = buf_get_u32(field.in_value, 0, 32);
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return ERROR_OK;
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}
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static int mips_ejtag_get_impcode(struct mips_ejtag *ejtag_info, uint32_t *impcode)
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{
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struct scan_field field;
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uint8_t r[4];
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_IMPCODE);
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field.num_bits = 32;
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field.out_value = NULL;
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field.in_value = r;
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jtag_add_dr_scan(ejtag_info->tap, 1, &field, TAP_IDLE);
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int retval;
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retval = jtag_execute_queue();
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if (retval != ERROR_OK) {
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LOG_ERROR("register read failed");
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return retval;
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}
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*impcode = buf_get_u32(field.in_value, 0, 32);
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return ERROR_OK;
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}
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void mips_ejtag_add_scan_96(struct mips_ejtag *ejtag_info, uint32_t ctrl, uint32_t data, uint8_t *in_scan_buf)
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{
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assert(ejtag_info->tap != NULL);
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struct jtag_tap *tap = ejtag_info->tap;
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struct scan_field field;
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uint8_t out_scan[12];
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/* processor access "all" register 96 bit */
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field.num_bits = 96;
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field.out_value = out_scan;
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buf_set_u32(out_scan, 0, 32, ctrl);
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buf_set_u32(out_scan + 4, 0, 32, data);
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buf_set_u32(out_scan + 8, 0, 32, 0);
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field.in_value = in_scan_buf;
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jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
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keep_alive();
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}
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void mips_ejtag_drscan_32_queued(struct mips_ejtag *ejtag_info, uint32_t data_out, uint8_t *data_in)
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{
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assert(ejtag_info->tap != NULL);
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struct jtag_tap *tap = ejtag_info->tap;
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struct scan_field field;
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field.num_bits = 32;
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uint8_t scan_out[4];
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field.out_value = scan_out;
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buf_set_u32(scan_out, 0, field.num_bits, data_out);
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field.in_value = data_in;
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jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
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keep_alive();
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}
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int mips_ejtag_drscan_32(struct mips_ejtag *ejtag_info, uint32_t *data)
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{
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uint8_t scan_in[4];
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mips_ejtag_drscan_32_queued(ejtag_info, *data, scan_in);
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int retval = jtag_execute_queue();
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if (retval != ERROR_OK) {
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LOG_ERROR("register read failed");
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return retval;
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}
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*data = buf_get_u32(scan_in, 0, 32);
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return ERROR_OK;
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}
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void mips_ejtag_drscan_32_out(struct mips_ejtag *ejtag_info, uint32_t data)
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{
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mips_ejtag_drscan_32_queued(ejtag_info, data, NULL);
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}
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int mips_ejtag_drscan_8(struct mips_ejtag *ejtag_info, uint8_t *data)
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{
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assert(ejtag_info->tap != NULL);
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struct jtag_tap *tap = ejtag_info->tap;
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struct scan_field field;
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field.num_bits = 8;
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field.out_value = data;
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field.in_value = data;
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jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
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int retval = jtag_execute_queue();
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if (retval != ERROR_OK) {
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LOG_ERROR("register read failed");
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return retval;
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}
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return ERROR_OK;
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}
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void mips_ejtag_drscan_8_out(struct mips_ejtag *ejtag_info, uint8_t data)
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{
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assert(ejtag_info->tap != NULL);
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struct jtag_tap *tap = ejtag_info->tap;
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struct scan_field field;
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field.num_bits = 8;
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field.out_value = &data;
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field.in_value = NULL;
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jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
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}
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/* Set (to enable) or clear (to disable stepping) the SSt bit (bit 8) in Cp0 Debug reg (reg 23, sel 0) */
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int mips_ejtag_config_step(struct mips_ejtag *ejtag_info, int enable_step)
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{
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struct pracc_queue_info ctx = {.ejtag_info = ejtag_info};
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pracc_queue_init(&ctx);
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pracc_add(&ctx, 0, MIPS32_MFC0(ctx.isa, 8, 23, 0)); /* move COP0 Debug to $8 */
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pracc_add(&ctx, 0, MIPS32_ORI(ctx.isa, 8, 8, 0x0100)); /* set SSt bit in debug reg */
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if (!enable_step)
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pracc_add(&ctx, 0, MIPS32_XORI(ctx.isa, 8, 8, 0x0100)); /* clear SSt bit in debug reg */
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pracc_add(&ctx, 0, MIPS32_MTC0(ctx.isa, 8, 23, 0)); /* move $8 to COP0 Debug */
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pracc_add(&ctx, 0, MIPS32_LUI(ctx.isa, 8, UPPER16(ejtag_info->reg8))); /* restore upper 16 bits of $8 */
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pracc_add(&ctx, 0, MIPS32_B(ctx.isa, NEG16((ctx.code_count + 1) << ctx.isa))); /* jump to start */
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pracc_add(&ctx, 0, MIPS32_ORI(ctx.isa, 8, 8, LOWER16(ejtag_info->reg8))); /* restore lower 16 bits of $8 */
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ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, NULL, 1);
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pracc_queue_free(&ctx);
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return ctx.retval;
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}
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/*
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* Disable memory protection for 0xFF20.0000–0xFF3F.FFFF
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* It is needed by EJTAG 1.5-2.0, especially for BMIPS CPUs
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* For example bcm7401 and others. At leas on some
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* CPUs, DebugMode wont start if this bit is not removed.
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*/
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static int disable_dcr_mp(struct mips_ejtag *ejtag_info)
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{
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uint32_t dcr;
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int retval;
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retval = mips32_dmaacc_read_mem(ejtag_info, EJTAG_DCR, 4, 1, &dcr);
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if (retval != ERROR_OK)
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goto error;
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dcr &= ~EJTAG_DCR_MP;
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retval = mips32_dmaacc_write_mem(ejtag_info, EJTAG_DCR, 4, 1, &dcr);
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if (retval != ERROR_OK)
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goto error;
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return ERROR_OK;
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error:
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LOG_ERROR("Failed to remove DCR MPbit!");
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return retval;
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}
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int mips_ejtag_enter_debug(struct mips_ejtag *ejtag_info)
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{
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uint32_t ejtag_ctrl;
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
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if (ejtag_info->ejtag_version == EJTAG_VERSION_20) {
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if (disable_dcr_mp(ejtag_info) != ERROR_OK)
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goto error;
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}
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/* set debug break bit */
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ejtag_ctrl = ejtag_info->ejtag_ctrl | EJTAG_CTRL_JTAGBRK;
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mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
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/* break bit will be cleared by hardware */
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ejtag_ctrl = ejtag_info->ejtag_ctrl;
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mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
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LOG_DEBUG("ejtag_ctrl: 0x%8.8" PRIx32 "", ejtag_ctrl);
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if ((ejtag_ctrl & EJTAG_CTRL_BRKST) == 0)
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goto error;
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return ERROR_OK;
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error:
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LOG_ERROR("Failed to enter Debug Mode!");
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return ERROR_FAIL;
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}
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int mips_ejtag_exit_debug(struct mips_ejtag *ejtag_info)
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{
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pa_list pracc_list = {.instr = MIPS32_DRET(ejtag_info->isa), .addr = 0};
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struct pracc_queue_info ctx = {.max_code = 1, .pracc_list = &pracc_list, .code_count = 1, .store_count = 0};
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/* execute our dret instruction */
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ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, NULL, 0); /* shift out instr, omit last check */
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/* pic32mx workaround, false pending at low core clock */
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jtag_add_sleep(1000);
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return ctx.retval;
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}
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/* mips_ejtag_init_mmr - asign Memory-Mapped Registers depending
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* on EJTAG version.
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*/
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static void mips_ejtag_init_mmr(struct mips_ejtag *ejtag_info)
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{
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if (ejtag_info->ejtag_version == EJTAG_VERSION_20) {
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ejtag_info->ejtag_ibs_addr = EJTAG_V20_IBS;
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ejtag_info->ejtag_iba0_addr = EJTAG_V20_IBA0;
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ejtag_info->ejtag_ibc_offs = EJTAG_V20_IBC_OFFS;
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ejtag_info->ejtag_ibm_offs = EJTAG_V20_IBM_OFFS;
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ejtag_info->ejtag_dbs_addr = EJTAG_V20_DBS;
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ejtag_info->ejtag_dba0_addr = EJTAG_V20_DBA0;
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ejtag_info->ejtag_dbc_offs = EJTAG_V20_DBC_OFFS;
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ejtag_info->ejtag_dbm_offs = EJTAG_V20_DBM_OFFS;
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ejtag_info->ejtag_dbv_offs = EJTAG_V20_DBV_OFFS;
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ejtag_info->ejtag_iba_step_size = EJTAG_V20_IBAn_STEP;
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ejtag_info->ejtag_dba_step_size = EJTAG_V20_DBAn_STEP;
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} else {
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ejtag_info->ejtag_ibs_addr = EJTAG_V25_IBS;
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ejtag_info->ejtag_iba0_addr = EJTAG_V25_IBA0;
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ejtag_info->ejtag_ibm_offs = EJTAG_V25_IBM_OFFS;
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ejtag_info->ejtag_ibasid_offs = EJTAG_V25_IBASID_OFFS;
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ejtag_info->ejtag_ibc_offs = EJTAG_V25_IBC_OFFS;
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ejtag_info->ejtag_dbs_addr = EJTAG_V25_DBS;
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ejtag_info->ejtag_dba0_addr = EJTAG_V25_DBA0;
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ejtag_info->ejtag_dbm_offs = EJTAG_V25_DBM_OFFS;
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ejtag_info->ejtag_dbasid_offs = EJTAG_V25_DBASID_OFFS;
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ejtag_info->ejtag_dbc_offs = EJTAG_V25_DBC_OFFS;
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ejtag_info->ejtag_dbv_offs = EJTAG_V25_DBV_OFFS;
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ejtag_info->ejtag_iba_step_size = EJTAG_V25_IBAn_STEP;
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ejtag_info->ejtag_dba_step_size = EJTAG_V25_DBAn_STEP;
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}
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}
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static void ejtag_v20_print_imp(struct mips_ejtag *ejtag_info)
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{
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LOG_DEBUG("EJTAG v2.0: features:%s%s%s%s%s%s%s%s",
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EJTAG_IMP_HAS(EJTAG_V20_IMP_SDBBP) ? " SDBBP_SPECIAL2" : " SDBBP",
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EJTAG_IMP_HAS(EJTAG_V20_IMP_EADDR_NO32BIT) ? " EADDR>32bit" : " EADDR=32bit",
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EJTAG_IMP_HAS(EJTAG_V20_IMP_COMPLEX_BREAK) ? " COMPLEX_BREAK" : "",
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EJTAG_IMP_HAS(EJTAG_V20_IMP_DCACHE_COH) ? " DCACHE_COH" : " DCACHE_NOT_COH",
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EJTAG_IMP_HAS(EJTAG_V20_IMP_ICACHE_COH) ? " ICACHE_COH" : " ICACHE_NOT_COH",
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EJTAG_IMP_HAS(EJTAG_V20_IMP_NOPB) ? " noPB" : " PB",
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EJTAG_IMP_HAS(EJTAG_V20_IMP_NODB) ? " noDB" : " DB",
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EJTAG_IMP_HAS(EJTAG_V20_IMP_NOIB) ? " noIB" : " IB");
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LOG_DEBUG("EJTAG v2.0: Break Channels: %" PRIu8,
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(uint8_t)((ejtag_info->impcode >> EJTAG_V20_IMP_BCHANNELS_SHIFT) &
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EJTAG_V20_IMP_BCHANNELS_MASK));
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}
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static void ejtag_v26_print_imp(struct mips_ejtag *ejtag_info)
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{
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LOG_DEBUG("EJTAG v2.6: features:%s%s",
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EJTAG_IMP_HAS(EJTAG_V26_IMP_R3K) ? " R3k" : " R4k",
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EJTAG_IMP_HAS(EJTAG_V26_IMP_DINT) ? " DINT" : "");
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}
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static void ejtag_main_print_imp(struct mips_ejtag *ejtag_info)
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{
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LOG_DEBUG("EJTAG main: features:%s%s%s%s%s",
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EJTAG_IMP_HAS(EJTAG_IMP_ASID8) ? " ASID_8" : "",
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EJTAG_IMP_HAS(EJTAG_IMP_ASID6) ? " ASID_6" : "",
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EJTAG_IMP_HAS(EJTAG_IMP_MIPS16) ? " MIPS16" : "",
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EJTAG_IMP_HAS(EJTAG_IMP_NODMA) ? " noDMA" : " DMA",
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EJTAG_IMP_HAS(EJTAG_DCR_MIPS64) ? " MIPS64" : " MIPS32");
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switch (ejtag_info->ejtag_version) {
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case EJTAG_VERSION_20:
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ejtag_v20_print_imp(ejtag_info);
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break;
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case EJTAG_VERSION_25:
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case EJTAG_VERSION_26:
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case EJTAG_VERSION_31:
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case EJTAG_VERSION_41:
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case EJTAG_VERSION_51:
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ejtag_v26_print_imp(ejtag_info);
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break;
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default:
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break;
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}
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}
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int mips_ejtag_init(struct mips_ejtag *ejtag_info)
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{
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int retval;
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retval = mips_ejtag_get_impcode(ejtag_info, &ejtag_info->impcode);
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if (retval != ERROR_OK)
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return retval;
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LOG_DEBUG("impcode: 0x%8.8" PRIx32 "", ejtag_info->impcode);
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/* get ejtag version */
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ejtag_info->ejtag_version = ((ejtag_info->impcode >> 29) & 0x07);
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switch (ejtag_info->ejtag_version) {
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case EJTAG_VERSION_20:
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LOG_DEBUG("EJTAG: Version 1 or 2.0 Detected");
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break;
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case EJTAG_VERSION_25:
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LOG_DEBUG("EJTAG: Version 2.5 Detected");
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break;
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case EJTAG_VERSION_26:
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LOG_DEBUG("EJTAG: Version 2.6 Detected");
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break;
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case EJTAG_VERSION_31:
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LOG_DEBUG("EJTAG: Version 3.1 Detected");
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break;
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case EJTAG_VERSION_41:
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LOG_DEBUG("EJTAG: Version 4.1 Detected");
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break;
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case EJTAG_VERSION_51:
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LOG_DEBUG("EJTAG: Version 5.1 Detected");
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break;
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default:
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LOG_DEBUG("EJTAG: Unknown Version Detected");
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break;
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}
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ejtag_main_print_imp(ejtag_info);
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if ((ejtag_info->impcode & EJTAG_IMP_NODMA) == 0) {
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LOG_DEBUG("EJTAG: DMA Access Mode detected. Disabling to "
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"workaround current broken code.");
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ejtag_info->impcode |= EJTAG_IMP_NODMA;
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}
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ejtag_info->ejtag_ctrl = EJTAG_CTRL_PRACC | EJTAG_CTRL_PROBEN;
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if (ejtag_info->ejtag_version != EJTAG_VERSION_20)
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ejtag_info->ejtag_ctrl |= EJTAG_CTRL_ROCC | EJTAG_CTRL_SETDEV;
|
||
|
||
ejtag_info->fast_access_save = -1;
|
||
|
||
mips_ejtag_init_mmr(ejtag_info);
|
||
|
||
return ERROR_OK;
|
||
}
|
||
|
||
int mips_ejtag_fastdata_scan(struct mips_ejtag *ejtag_info, int write_t, uint32_t *data)
|
||
{
|
||
assert(ejtag_info->tap != NULL);
|
||
struct jtag_tap *tap = ejtag_info->tap;
|
||
|
||
struct scan_field fields[2];
|
||
|
||
/* fastdata 1-bit register */
|
||
fields[0].num_bits = 1;
|
||
|
||
uint8_t spracc = 0;
|
||
fields[0].out_value = &spracc;
|
||
fields[0].in_value = NULL;
|
||
|
||
/* processor access data register 32 bit */
|
||
fields[1].num_bits = 32;
|
||
|
||
uint8_t t[4] = {0, 0, 0, 0};
|
||
fields[1].out_value = t;
|
||
|
||
if (write_t) {
|
||
fields[1].in_value = NULL;
|
||
buf_set_u32(t, 0, 32, *data);
|
||
} else
|
||
fields[1].in_value = (uint8_t *) data;
|
||
|
||
jtag_add_dr_scan(tap, 2, fields, TAP_IDLE);
|
||
|
||
if (!write_t && data)
|
||
jtag_add_callback(mips_le_to_h_u32,
|
||
(jtag_callback_data_t) data);
|
||
|
||
keep_alive();
|
||
|
||
return ERROR_OK;
|
||
}
|