194 lines
6.8 KiB
C
194 lines
6.8 KiB
C
/***************************************************************************
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* Copyright (C) 2013 by Andes Technology *
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* Hsiangkai Wang <hkwang@andestech.com> *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, write to the *
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* Free Software Foundation, Inc., *
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
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***************************************************************************/
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#ifndef __AICE_USB_H__
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#define __AICE_USB_H__
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#include "aice_port.h"
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/* AICE USB timeout value */
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#define AICE_USB_TIMEOUT 5000
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/* AICE USB buffer size */
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#define AICE_IN_BUFFER_SIZE 2048
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#define AICE_OUT_BUFFER_SIZE 2048
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#define AICE_IN_PACKETS_BUFFER_SIZE 2048
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#define AICE_OUT_PACKETS_BUFFER_SIZE 2048
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#define AICE_IN_BATCH_COMMAND_SIZE 512
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#define AICE_OUT_BATCH_COMMAND_SIZE 512
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#define AICE_IN_PACK_COMMAND_SIZE 2048
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#define AICE_OUT_PACK_COMMAND_SIZE 2048
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/* Constants for AICE command */
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#define AICE_CMD_SCAN_CHAIN 0x00
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#define AICE_CMD_SELECT_TARGET 0x01
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#define AICE_CMD_READ_DIM 0x02
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#define AICE_CMD_READ_EDMSR 0x03
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#define AICE_CMD_READ_DTR 0x04
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#define AICE_CMD_READ_MEM 0x05
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#define AICE_CMD_READ_MISC 0x06
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#define AICE_CMD_FASTREAD_MEM 0x07
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#define AICE_CMD_WRITE_DIM 0x08
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#define AICE_CMD_WRITE_EDMSR 0x09
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#define AICE_CMD_WRITE_DTR 0x0A
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#define AICE_CMD_WRITE_MEM 0x0B
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#define AICE_CMD_WRITE_MISC 0x0C
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#define AICE_CMD_FASTWRITE_MEM 0x0D
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#define AICE_CMD_EXECUTE 0x0E
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#define AICE_CMD_READ_MEM_B 0x14
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#define AICE_CMD_READ_MEM_H 0x15
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#define AICE_CMD_T_READ_MISC 0x20
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#define AICE_CMD_T_READ_EDMSR 0x21
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#define AICE_CMD_T_READ_DTR 0x22
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#define AICE_CMD_T_READ_DIM 0x23
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#define AICE_CMD_T_READ_MEM_B 0x24
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#define AICE_CMD_T_READ_MEM_H 0x25
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#define AICE_CMD_T_READ_MEM 0x26
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#define AICE_CMD_T_FASTREAD_MEM 0x27
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#define AICE_CMD_T_WRITE_MISC 0x28
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#define AICE_CMD_T_WRITE_EDMSR 0x29
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#define AICE_CMD_T_WRITE_DTR 0x2A
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#define AICE_CMD_T_WRITE_DIM 0x2B
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#define AICE_CMD_T_WRITE_MEM_B 0x2C
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#define AICE_CMD_T_WRITE_MEM_H 0x2D
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#define AICE_CMD_T_WRITE_MEM 0x2E
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#define AICE_CMD_T_FASTWRITE_MEM 0x2F
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#define AICE_CMD_T_GET_TRACE_STATUS 0x36
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#define AICE_CMD_T_EXECUTE 0x3E
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#define AICE_CMD_AICE_PROGRAM_READ 0x40
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#define AICE_CMD_AICE_PROGRAM_WRITE 0x41
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#define AICE_CMD_AICE_PROGRAM_CONTROL 0x42
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#define AICE_CMD_READ_CTRL 0x50
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#define AICE_CMD_WRITE_CTRL 0x51
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#define AICE_CMD_BATCH_BUFFER_READ 0x60
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#define AICE_CMD_READ_DTR_TO_BUFFER 0x61
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#define AICE_CMD_BATCH_BUFFER_WRITE 0x68
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#define AICE_CMD_WRITE_DTR_FROM_BUFFER 0x69
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/* Constants for AICE command format length */
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#define AICE_FORMAT_HTDA 3
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#define AICE_FORMAT_HTDB 6
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#define AICE_FORMAT_HTDC 7
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#define AICE_FORMAT_HTDD 10
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#define AICE_FORMAT_HTDMA 4
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#define AICE_FORMAT_HTDMB 8
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#define AICE_FORMAT_HTDMC 8
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#define AICE_FORMAT_HTDMD 12
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#define AICE_FORMAT_DTHA 6
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#define AICE_FORMAT_DTHB 2
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#define AICE_FORMAT_DTHMA 8
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#define AICE_FORMAT_DTHMB 4
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/* Constants for AICE command READ_CTRL */
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#define AICE_READ_CTRL_GET_ICE_STATE 0x00
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#define AICE_READ_CTRL_GET_HARDWARE_VERSION 0x01
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#define AICE_READ_CTRL_GET_FPGA_VERSION 0x02
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#define AICE_READ_CTRL_GET_FIRMWARE_VERSION 0x03
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#define AICE_READ_CTRL_GET_JTAG_PIN_STATUS 0x04
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#define AICE_READ_CTRL_BATCH_BUF_INFO 0x22
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#define AICE_READ_CTRL_BATCH_STATUS 0x23
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#define AICE_READ_CTRL_BATCH_BUF0_STATE 0x31
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#define AICE_READ_CTRL_BATCH_BUF4_STATE 0x39
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#define AICE_READ_CTRL_BATCH_BUF5_STATE 0x3b
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/* Constants for AICE command WRITE_CTRL */
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#define AICE_WRITE_CTRL_TCK_CONTROL 0x00
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#define AICE_WRITE_CTRL_JTAG_PIN_CONTROL 0x01
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#define AICE_WRITE_CTRL_CLEAR_TIMEOUT_STATUS 0x02
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#define AICE_WRITE_CTRL_RESERVED 0x03
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#define AICE_WRITE_CTRL_JTAG_PIN_STATUS 0x04
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#define AICE_WRITE_CTRL_CUSTOM_DELAY 0x0d
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#define AICE_WRITE_CTRL_BATCH_CTRL 0x20
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#define AICE_WRITE_CTRL_BATCH_ITERATION 0x21
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#define AICE_WRITE_CTRL_BATCH_DIM_SIZE 0x22
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#define AICE_WRITE_CTRL_BATCH_CMD_BUF0_CTRL 0x30
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#define AICE_WRITE_CTRL_BATCH_DATA_BUF0_CTRL 0x38
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#define AICE_WRITE_CTRL_BATCH_DATA_BUF1_CTRL 0x3a
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#define AICE_BATCH_COMMAND_BUFFER_0 0x0
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#define AICE_BATCH_COMMAND_BUFFER_1 0x1
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#define AICE_BATCH_COMMAND_BUFFER_2 0x2
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#define AICE_BATCH_COMMAND_BUFFER_3 0x3
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#define AICE_BATCH_DATA_BUFFER_0 0x4
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#define AICE_BATCH_DATA_BUFFER_1 0x5
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#define AICE_BATCH_DATA_BUFFER_2 0x6
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#define AICE_BATCH_DATA_BUFFER_3 0x7
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/* Constants for AICE command WRITE_CTRL:TCK_CONTROL */
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#define AICE_TCK_CONTROL_TCK3048 0x08
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/* Constants for AICE command WRITE_CTRL:JTAG_PIN_CONTROL */
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#define AICE_JTAG_PIN_CONTROL_SRST 0x01
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#define AICE_JTAG_PIN_CONTROL_TRST 0x02
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#define AICE_JTAG_PIN_CONTROL_STOP 0x04
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#define AICE_JTAG_PIN_CONTROL_RESTART 0x08
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/* Constants for AICE command WRITE_CTRL:TCK_CONTROL */
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#define AICE_TCK_CONTROL_TCK_SCAN 0x10
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/* Custom SRST/DBGI/TRST */
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#define AICE_CUSTOM_DELAY_SET_SRST 0x01
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#define AICE_CUSTOM_DELAY_CLEAN_SRST 0x02
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#define AICE_CUSTOM_DELAY_SET_DBGI 0x04
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#define AICE_CUSTOM_DELAY_CLEAN_DBGI 0x08
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#define AICE_CUSTOM_DELAY_SET_TRST 0x10
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#define AICE_CUSTOM_DELAY_CLEAN_TRST 0x20
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struct aice_usb_handler_s {
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unsigned int usb_read_ep;
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unsigned int usb_write_ep;
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struct jtag_libusb_device_handle *usb_handle;
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};
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struct cache_info {
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uint32_t set;
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uint32_t way;
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uint32_t line_size;
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uint32_t log2_set;
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uint32_t log2_line_size;
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};
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struct aice_nds32_info {
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uint32_t edm_version;
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uint32_t r0_backup;
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uint32_t r1_backup;
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uint32_t host_dtr_backup;
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uint32_t target_dtr_backup;
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uint32_t edmsw_backup;
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uint32_t edm_ctl_backup;
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bool debug_under_dex_on;
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bool dex_use_psw_on;
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bool host_dtr_valid;
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bool target_dtr_valid;
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enum nds_memory_access access_channel;
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enum nds_memory_select memory_select;
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enum aice_target_state_s core_state;
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bool cache_init;
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struct cache_info icache;
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struct cache_info dcache;
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};
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extern struct aice_port_api_s aice_usb_api;
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int aice_read_ctrl(uint32_t address, uint32_t *data);
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int aice_write_ctrl(uint32_t address, uint32_t data);
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#endif
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