264d24495d
Changes from the flat namespace to heirarchical one. Instead of writing: #include "command.h" the following form should be used. #include <helper/command.h> The exception is from .c files in the same directory.
376 lines
12 KiB
C
376 lines
12 KiB
C
/***************************************************************************
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* Copyright (C) 2005 by Dominic Rath *
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* Dominic.Rath@gmx.de *
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* *
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* Copyright (C) 2008 by Spencer Oliver *
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* spen@spen-soft.co.uk *
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* *
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* Copyright (C) 2009 by Øyvind Harboe *
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* oyvind.harboe@zylin.com *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, write to the *
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* Free Software Foundation, Inc., *
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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***************************************************************************/
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#ifndef ARMV4_5_H
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#define ARMV4_5_H
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#include "target.h"
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#include <helper/command.h>
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typedef enum armv4_5_mode
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{
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ARMV4_5_MODE_USR = 16,
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ARMV4_5_MODE_FIQ = 17,
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ARMV4_5_MODE_IRQ = 18,
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ARMV4_5_MODE_SVC = 19,
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ARMV4_5_MODE_ABT = 23,
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ARM_MODE_MON = 26,
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ARMV4_5_MODE_UND = 27,
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ARMV4_5_MODE_SYS = 31,
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ARMV4_5_MODE_ANY = -1
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} armv4_5_mode_t;
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const char *arm_mode_name(unsigned psr_mode);
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bool is_arm_mode(unsigned psr_mode);
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int armv4_5_mode_to_number(enum armv4_5_mode mode);
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enum armv4_5_mode armv4_5_number_to_mode(int number);
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typedef enum armv4_5_state
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{
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ARMV4_5_STATE_ARM,
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ARMV4_5_STATE_THUMB,
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ARMV4_5_STATE_JAZELLE,
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ARM_STATE_THUMB_EE,
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} armv4_5_state_t;
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extern char* armv4_5_state_strings[];
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extern const int armv4_5_core_reg_map[8][17];
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#define ARMV4_5_CORE_REG_MODE(cache, mode, num) \
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cache->reg_list[armv4_5_core_reg_map[armv4_5_mode_to_number(mode)][num]]
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/* offset into armv4_5 core register cache -- OBSOLETE, DO NOT USE! */
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enum { ARMV4_5_CPSR = 31, };
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#define ARMV4_5_COMMON_MAGIC 0x0A450A45
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/**
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* Represents a generic ARM core, with standard application registers.
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*
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* There are sixteen application registers (including PC, SP, LR) and a PSR.
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* Cortex-M series cores do not support as many core states or shadowed
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* registers as traditional ARM cores, and only support Thumb2 instructions.
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*/
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struct arm
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{
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int common_magic;
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struct reg_cache *core_cache;
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/** Handle to the CPSR; valid in all core modes. */
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struct reg *cpsr;
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/** Handle to the SPSR; valid only in core modes with an SPSR. */
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struct reg *spsr;
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const int *map;
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/**
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* Indicates what registers are in the ARM state core register set.
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* ARMV4_5_MODE_ANY indicates the standard set of 37 registers,
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* seen on for example ARM7TDMI cores. ARM_MODE_MON indicates three
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* more registers are shadowed, for "Secure Monitor" mode.
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*/
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enum armv4_5_mode core_type;
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enum armv4_5_mode core_mode;
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enum armv4_5_state core_state;
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/** Flag reporting unavailability of the BKPT instruction. */
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bool is_armv4;
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/** Backpointer to the target. */
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struct target *target;
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/** Handle for the debug module, if one is present. */
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struct arm_dpm *dpm;
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/** Handle for the Embedded Trace Module, if one is present. */
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struct etm_context *etm;
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/* FIXME all these methods should take "struct arm *" not target */
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int (*full_context)(struct target *target);
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int (*read_core_reg)(struct target *target, struct reg *reg,
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int num, enum armv4_5_mode mode);
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int (*write_core_reg)(struct target *target, struct reg *reg,
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int num, enum armv4_5_mode mode, uint32_t value);
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/** Read coprocessor register. */
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int (*mrc)(struct target *target, int cpnum,
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uint32_t op1, uint32_t op2,
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uint32_t CRn, uint32_t CRm,
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uint32_t *value);
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/* Write coprocessor register. */
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int (*mcr)(struct target *target, int cpnum,
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uint32_t op1, uint32_t op2,
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uint32_t CRn, uint32_t CRm,
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uint32_t value);
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void *arch_info;
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};
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#define target_to_armv4_5 target_to_arm
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/** Convert target handle to generic ARM target state handle. */
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static inline struct arm *target_to_arm(struct target *target)
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{
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return target->arch_info;
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}
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static inline bool is_arm(struct arm *arm)
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{
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return arm && arm->common_magic == ARMV4_5_COMMON_MAGIC;
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}
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struct armv4_5_algorithm
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{
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int common_magic;
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enum armv4_5_mode core_mode;
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enum armv4_5_state core_state;
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};
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struct arm_reg
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{
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int num;
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enum armv4_5_mode mode;
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struct target *target;
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struct arm *armv4_5_common;
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uint32_t value;
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};
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struct reg_cache* armv4_5_build_reg_cache(struct target *target,
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struct arm *armv4_5_common);
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int armv4_5_arch_state(struct target *target);
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int armv4_5_get_gdb_reg_list(struct target *target,
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struct reg **reg_list[], int *reg_list_size);
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extern const struct command_registration arm_command_handlers[];
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int armv4_5_init_arch_info(struct target *target, struct arm *armv4_5);
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int armv4_5_run_algorithm(struct target *target,
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int num_mem_params, struct mem_param *mem_params,
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int num_reg_params, struct reg_param *reg_params,
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uint32_t entry_point, uint32_t exit_point,
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int timeout_ms, void *arch_info);
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int arm_checksum_memory(struct target *target,
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uint32_t address, uint32_t count, uint32_t *checksum);
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int arm_blank_check_memory(struct target *target,
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uint32_t address, uint32_t count, uint32_t *blank);
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void arm_set_cpsr(struct arm *arm, uint32_t cpsr);
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struct reg *arm_reg_current(struct arm *arm, unsigned regnum);
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extern struct reg arm_gdb_dummy_fp_reg;
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extern struct reg arm_gdb_dummy_fps_reg;
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/* ARM mode instructions
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*/
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/* Store multiple increment after
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* Rn: base register
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* List: for each bit in list: store register
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* S: in priviledged mode: store user-mode registers
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* W = 1: update the base register. W = 0: leave the base register untouched
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*/
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#define ARMV4_5_STMIA(Rn, List, S, W) (0xe8800000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List))
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/* Load multiple increment after
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* Rn: base register
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* List: for each bit in list: store register
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* S: in priviledged mode: store user-mode registers
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* W = 1: update the base register. W = 0: leave the base register untouched
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*/
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#define ARMV4_5_LDMIA(Rn, List, S, W) (0xe8900000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List))
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/* MOV r8, r8 */
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#define ARMV4_5_NOP (0xe1a08008)
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/* Move PSR to general purpose register
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* R = 1: SPSR R = 0: CPSR
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* Rn: target register
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*/
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#define ARMV4_5_MRS(Rn, R) (0xe10f0000 | ((R) << 22) | ((Rn) << 12))
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/* Store register
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* Rd: register to store
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* Rn: base register
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*/
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#define ARMV4_5_STR(Rd, Rn) (0xe5800000 | ((Rd) << 12) | ((Rn) << 16))
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/* Load register
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* Rd: register to load
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* Rn: base register
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*/
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#define ARMV4_5_LDR(Rd, Rn) (0xe5900000 | ((Rd) << 12) | ((Rn) << 16))
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/* Move general purpose register to PSR
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* R = 1: SPSR R = 0: CPSR
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* Field: Field mask
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* 1: control field 2: extension field 4: status field 8: flags field
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* Rm: source register
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*/
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#define ARMV4_5_MSR_GP(Rm, Field, R) (0xe120f000 | (Rm) | ((Field) << 16) | ((R) << 22))
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#define ARMV4_5_MSR_IM(Im, Rotate, Field, R) (0xe320f000 | (Im) | ((Rotate) << 8) | ((Field) << 16) | ((R) << 22))
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/* Load Register Halfword Immediate Post-Index
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* Rd: register to load
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* Rn: base register
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*/
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#define ARMV4_5_LDRH_IP(Rd, Rn) (0xe0d000b2 | ((Rd) << 12) | ((Rn) << 16))
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/* Load Register Byte Immediate Post-Index
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* Rd: register to load
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* Rn: base register
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*/
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#define ARMV4_5_LDRB_IP(Rd, Rn) (0xe4d00001 | ((Rd) << 12) | ((Rn) << 16))
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/* Store register Halfword Immediate Post-Index
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* Rd: register to store
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* Rn: base register
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*/
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#define ARMV4_5_STRH_IP(Rd, Rn) (0xe0c000b2 | ((Rd) << 12) | ((Rn) << 16))
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/* Store register Byte Immediate Post-Index
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* Rd: register to store
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* Rn: base register
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*/
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#define ARMV4_5_STRB_IP(Rd, Rn) (0xe4c00001 | ((Rd) << 12) | ((Rn) << 16))
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/* Branch (and Link)
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* Im: Branch target (left-shifted by 2 bits, added to PC)
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* L: 1: branch and link 0: branch only
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*/
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#define ARMV4_5_B(Im, L) (0xea000000 | (Im) | ((L) << 24))
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/* Branch and exchange (ARM state)
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* Rm: register holding branch target address
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*/
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#define ARMV4_5_BX(Rm) (0xe12fff10 | (Rm))
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/* Move to ARM register from coprocessor
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* CP: Coprocessor number
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* op1: Coprocessor opcode
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* Rd: destination register
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* CRn: first coprocessor operand
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* CRm: second coprocessor operand
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* op2: Second coprocessor opcode
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*/
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#define ARMV4_5_MRC(CP, op1, Rd, CRn, CRm, op2) (0xee100010 | (CRm) | ((op2) << 5) | ((CP) << 8) | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21))
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/* Move to coprocessor from ARM register
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* CP: Coprocessor number
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* op1: Coprocessor opcode
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* Rd: destination register
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* CRn: first coprocessor operand
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* CRm: second coprocessor operand
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* op2: Second coprocessor opcode
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*/
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#define ARMV4_5_MCR(CP, op1, Rd, CRn, CRm, op2) (0xee000010 | (CRm) | ((op2) << 5) | ((CP) << 8) | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21))
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/* Breakpoint instruction (ARMv5)
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* Im: 16-bit immediate
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*/
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#define ARMV5_BKPT(Im) (0xe1200070 | ((Im & 0xfff0) << 8) | (Im & 0xf))
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/* Thumb mode instructions
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*/
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/* Store register (Thumb mode)
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* Rd: source register
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* Rn: base register
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*/
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#define ARMV4_5_T_STR(Rd, Rn) ((0x6000 | (Rd) | ((Rn) << 3)) | ((0x6000 | (Rd) | ((Rn) << 3)) << 16))
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/* Load register (Thumb state)
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* Rd: destination register
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* Rn: base register
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*/
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#define ARMV4_5_T_LDR(Rd, Rn) ((0x6800 | ((Rn) << 3) | (Rd)) | ((0x6800 | ((Rn) << 3) | (Rd)) << 16))
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/* Load multiple (Thumb state)
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* Rn: base register
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* List: for each bit in list: store register
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*/
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#define ARMV4_5_T_LDMIA(Rn, List) ((0xc800 | ((Rn) << 8) | (List)) | ((0xc800 | ((Rn) << 8) | List) << 16))
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/* Load register with PC relative addressing
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* Rd: register to load
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*/
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#define ARMV4_5_T_LDR_PCREL(Rd) ((0x4800 | ((Rd) << 8)) | ((0x4800 | ((Rd) << 8)) << 16))
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/* Move hi register (Thumb mode)
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* Rd: destination register
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* Rm: source register
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*/
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#define ARMV4_5_T_MOV(Rd, Rm) ((0x4600 | ((Rd) & 0x7) | (((Rd) & 0x8) << 4) | (((Rm) & 0x7) << 3) | (((Rm) & 0x8) << 3)) | ((0x4600 | ((Rd) & 0x7) | (((Rd) & 0x8) << 4) | (((Rm) & 0x7) << 3) | (((Rm) & 0x8) << 3)) << 16))
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/* No operation (Thumb mode)
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*/
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#define ARMV4_5_T_NOP (0x46c0 | (0x46c0 << 16))
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/* Move immediate to register (Thumb state)
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* Rd: destination register
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* Im: 8-bit immediate value
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*/
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#define ARMV4_5_T_MOV_IM(Rd, Im) ((0x2000 | ((Rd) << 8) | (Im)) | ((0x2000 | ((Rd) << 8) | (Im)) << 16))
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/* Branch and Exchange
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* Rm: register containing branch target
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*/
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#define ARMV4_5_T_BX(Rm) ((0x4700 | ((Rm) << 3)) | ((0x4700 | ((Rm) << 3)) << 16))
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/* Branch (Thumb state)
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* Imm: Branch target
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*/
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#define ARMV4_5_T_B(Imm) ((0xe000 | (Imm)) | ((0xe000 | (Imm)) << 16))
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/* Breakpoint instruction (ARMv5) (Thumb state)
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* Im: 8-bit immediate
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*/
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#define ARMV5_T_BKPT(Im) ((0xbe00 | Im) | ((0xbe00 | Im) << 16))
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/* build basic mrc/mcr opcode */
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static inline uint32_t mrc_opcode(int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm)
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{
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uint32_t t = 0;
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t|=op1<<21;
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t|=op2<<5;
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t|=CRn<<16;
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t|=CRm<<0;
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return t;
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}
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#endif /* ARMV4_5_H */
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