0da0bfd40a
This gets rid of runtime warnings from the use of numbers. STM32 and LPC2103 were tested. Other LPC updates are the same, and so are safe. The CFI updates match other tested changes now in the tree. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
51 lines
1.4 KiB
INI
51 lines
1.4 KiB
INI
# NXP LPC1768 Cortex-M3 with 512kB Flash and 32kB+32kB Local On-Chip SRAM, clocked with 4MHz internal RC oscillator
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME lpc1768
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}
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if { [info exists ENDIAN] } {
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set _ENDIAN $ENDIAN
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} else {
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set _ENDIAN little
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}
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if { [info exists CPUTAPID ] } {
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set _CPUTAPID $CPUTAPID
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} else {
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set _CPUTAPID 0x4ba00477
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}
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#delays on reset lines
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jtag_nsrst_delay 200
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jtag_ntrst_delay 200
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# LPC2000 & LPC1700 -> SRST causes TRST
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reset_config trst_and_srst srst_pulls_trst
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jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
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# LPC1768 has 32kB of SRAM on its main system bus (so-called Local On-Chip SRAM)
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$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x10000000 -work-area-size 0x8000 -work-area-backup 0
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$_TARGETNAME configure -event reset-init {
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# Force target into ARM state
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armv4_5 core_state arm
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#do not remap 0x0000-0x0020 to anything but the flash
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# mwb 0xE01FC040 0x01
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mwb 0xE000ED08 0x00
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}
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# LPC1768 has 512kB of user-available FLASH (bootloader is located in separate dedicated region).
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# flash bank lpc1700 <base> <size> 0 0 <target#> <variant> <cclk> [calc_checksum]
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flash bank lpc2000 0x0 0x80000 0 0 $_TARGETNAME lpc1700 12000 calc_checksum
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# 4MHz / 6 = 666kHz, so use 500
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jtag_khz 500
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