6cadbadb37
This is only the basic code proposed for mips32_pracc_exec() function. It checks every pracc address against the expected address when reading (instruction fetch). The code expects to start at PRACC_TEXT and any subsequent read address is obtained by adding 4 to the previous one. After shifting out all the instructions the code executes a final check. It checks now for the first pass trough PRACC_TEXT and shift out only NOP instructions. A mips core does not need an additional NOP and after the first check it exits if there is no store access pending. After shifting out one NOP the core must be reading at pracc text or the code exits with error. The code continues shifting out NOPs until all store accesses have been performed. After shifting out 10 NOPs it exits with error. No assumption is made about the number of store instruction shifted out or the ordering of the store accesses. It only checks that the number of store accesses is the same as the number of store instructions at dmseg after execution. mips32_pracc_read_ctrl_addr() and mips32_pracc_finish() are added to simpify a bit the code. Fields pa_ctrl and pa_addr are added in ejtag_info for storing values of pracc control and address. Change-Id: If6322d5c8cbeadcd4acd3972c0f72c8490f53c34 Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/1827 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
105 lines
4.5 KiB
C
105 lines
4.5 KiB
C
/***************************************************************************
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* Copyright (C) 2008 by Spencer Oliver *
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* spen@spen-soft.co.uk *
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* *
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* Copyright (C) 2008 by David T.L. Wong *
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* *
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* Copyright (C) 2011 by Drasko DRASKOVIC *
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* drasko.draskovic@gmail.com *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, write to the *
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* Free Software Foundation, Inc., *
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
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***************************************************************************/
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#ifndef MIPS32_PRACC_H
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#define MIPS32_PRACC_H
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#include <target/mips32.h>
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#include <target/mips_ejtag.h>
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#define MIPS32_PRACC_FASTDATA_AREA 0xFF200000
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#define MIPS32_PRACC_FASTDATA_SIZE 16
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#define MIPS32_PRACC_BASE_ADDR 0xFF200000
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#define MIPS32_PRACC_TEXT 0xFF200200
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#define MIPS32_PRACC_PARAM_OUT 0xFF202000
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#define PRACC_UPPER_BASE_ADDR (MIPS32_PRACC_BASE_ADDR >> 16)
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#define PRACC_OUT_OFFSET (MIPS32_PRACC_PARAM_OUT - MIPS32_PRACC_BASE_ADDR)
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#define MIPS32_FASTDATA_HANDLER_SIZE 0x80
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#define UPPER16(uint32_t) (uint32_t >> 16)
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#define LOWER16(uint32_t) (uint32_t & 0xFFFF)
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#define NEG16(v) (((~(v)) + 1) & 0xFFFF)
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/*#define NEG18(v) (((~(v)) + 1) & 0x3FFFF)*/
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struct pracc_queue_info {
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int retval;
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const int max_code;
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int code_count;
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int store_count;
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uint32_t *pracc_list; /* Code and store addresses */
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};
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void pracc_queue_init(struct pracc_queue_info *ctx);
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void pracc_add(struct pracc_queue_info *ctx, uint32_t addr, uint32_t instr);
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void pracc_queue_free(struct pracc_queue_info *ctx);
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int mips32_pracc_queue_exec(struct mips_ejtag *ejtag_info,
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struct pracc_queue_info *ctx, uint32_t *buf);
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int mips32_pracc_read_mem(struct mips_ejtag *ejtag_info,
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uint32_t addr, int size, int count, void *buf);
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int mips32_pracc_write_mem(struct mips_ejtag *ejtag_info,
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uint32_t addr, int size, int count, const void *buf);
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int mips32_pracc_fastdata_xfer(struct mips_ejtag *ejtag_info, struct working_area *source,
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int write_t, uint32_t addr, int count, uint32_t *buf);
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int mips32_pracc_read_regs(struct mips_ejtag *ejtag_info, uint32_t *regs);
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int mips32_pracc_write_regs(struct mips_ejtag *ejtag_info, uint32_t *regs);
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int mips32_pracc_exec(struct mips_ejtag *ejtag_info, struct pracc_queue_info *ctx, uint32_t *param_out);
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/**
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* \b mips32_cp0_read
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*
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* Simulates mfc0 ASM instruction (Move From C0),
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* i.e. implements copro C0 Register read.
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*
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* @param[in] ejtag_info
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* @param[in] val Storage to hold read value
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* @param[in] cp0_reg Number of copro C0 register we want to read
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* @param[in] cp0_sel Select for the given C0 register
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*
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* @return ERROR_OK on Sucess, ERROR_FAIL otherwise
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*/
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int mips32_cp0_read(struct mips_ejtag *ejtag_info,
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uint32_t *val, uint32_t cp0_reg, uint32_t cp0_sel);
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/**
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* \b mips32_cp0_write
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*
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* Simulates mtc0 ASM instruction (Move To C0),
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* i.e. implements copro C0 Register read.
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*
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* @param[in] ejtag_info
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* @param[in] val Value to be written
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* @param[in] cp0_reg Number of copro C0 register we want to write to
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* @param[in] cp0_sel Select for the given C0 register
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*
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* @return ERROR_OK on Sucess, ERROR_FAIL otherwise
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*/
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int mips32_cp0_write(struct mips_ejtag *ejtag_info,
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uint32_t val, uint32_t cp0_reg, uint32_t cp0_sel);
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#endif
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