e44539d66c
- write speed up to 150 kByte/s on STM32F469I-disco (due to SWD clock and USB connection), up to 1 MByte/s on Nucleo-F767ZI with external STLink-V3 or Nucleo-G474RE with two W25Q256FV in dual 4-line mode or STM32H73BI-Disco in octal mode - tested with STM32L476G-disco (64MBit flash, 3-byte addr), STM32F412G-Disco, STM32F469I-Disco, STM32F746G-Disco, and STM32L476G-Disco (all 128Mbit flash, 3-byte addr), STM32F723E-Disco, STM32F769I-Disco (512Mbit flash, 4-byte addr) STM32L4R9I-Disco, STM32L4P5G-Disco (512MBit octo-flash, DTR, 4-byte addr) STM32H745I-Disco, STM32H747I-Disco (two 512MBit flash, 4-byte addr) STM32H73BI-Disco, STM32H735G-Disco (512MBit octo-flash, DTR, 4-byte addr) - suitable cfg for Discovery boards included - limited parsing of SFDP data if flash device not hardcoded (tested only in single/quad mode as most devices either don't support SFDP at all or have empty(!) SFDP memory) - 'set' command for auto detection override (e. g. for EEPROMs) - 'cmd' command for arbitrary SPI commands (reconfiguration, testing etc.) - makefile for creation of binary loader files - tcl/board/stm32f469discovery.cfg superseded by stm32f469i-disco.cfg - tcl/board/stm32f7discovery.cfg removed as name is ambiguous (superseded by stm32f746g-disco.cfg vs. stm32f769i-disco.cfg) - dual 4-line mode tested on Nucleo-F767ZI, Nucleo-H743ZI and Nucleo-H7A3ZI-Q with two W25Q256FV, and on Nucleo-L496ZP-P and Nucleo-L4R5ZI with two W25Q128FV, sample cfg files included and on STM32H745I-Disco, STM32H747I-Disco, STM32H750B-Disco - read/verify/erase_check uses indirect read mode to work around silicon bug in H7, L4+ and MP1 memory mapped mode (last bytes not readable, accessing last bytes causes debug interface to hang) - octospi supported only in single/dual 1-line, 2-line, 4-line and single 8-line modes, (not in hyper flash mode) Requirements: GPIOs must be initialized appropriately, and SPI flash chip be configured appropriately (1-line ..., QPI, 4-byte addresses ...). This is board/chip specific, cf. included cfg files. The driver infers most parameters from current setting in CR, CCR, ... registers. Change-Id: I54858fbbe8758c3a5fe58812e93f5f39514704f8 Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com> Reviewed-on: http://openocd.zylin.com/4321 Tested-by: jenkins Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: Christopher Head <chead@zaber.com>
96 lines
3.9 KiB
C
96 lines
3.9 KiB
C
/***************************************************************************
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* Copyright (C) 2018-2019 by Andreas Bolsch *
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* andreas.bolsch@mni.thm.de *
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* *
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* Copyright (C) 2012 by George Harris *
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* george@luminairecoffee.com *
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* *
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* Copyright (C) 2010 by Antonio Borneo *
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* borneo.antonio@gmail.com *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program. If not, see <http://www.gnu.org/licenses/>. *
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***************************************************************************/
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#ifndef OPENOCD_FLASH_NOR_SPI_H
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#define OPENOCD_FLASH_NOR_SPI_H
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#ifndef __ASSEMBLER__
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/* data structure to maintain flash ids from different vendors */
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struct flash_device {
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const char *name;
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uint8_t read_cmd;
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uint8_t qread_cmd;
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uint8_t pprog_cmd;
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uint8_t erase_cmd;
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uint8_t chip_erase_cmd;
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uint32_t device_id;
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uint32_t pagesize;
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uint32_t sectorsize;
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uint32_t size_in_bytes;
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};
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#define FLASH_ID(n, re, qr, pp, es, ces, id, psize, ssize, size) \
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{ \
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.name = n, \
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.read_cmd = re, \
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.qread_cmd = qr, \
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.pprog_cmd = pp, \
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.erase_cmd = es, \
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.chip_erase_cmd = ces, \
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.device_id = id, \
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.pagesize = psize, \
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.sectorsize = ssize, \
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.size_in_bytes = size, \
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}
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#define FRAM_ID(n, re, qr, pp, id, size) \
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{ \
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.name = n, \
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.read_cmd = re, \
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.qread_cmd = qr, \
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.pprog_cmd = pp, \
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.erase_cmd = 0x00, \
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.chip_erase_cmd = 0x00, \
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.device_id = id, \
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.pagesize = 0, \
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.sectorsize = 0, \
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.size_in_bytes = size, \
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}
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extern const struct flash_device flash_devices[];
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#endif
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/* fields in SPI flash status register */
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#define SPIFLASH_BSY 0
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#define SPIFLASH_BSY_BIT (1 << SPIFLASH_BSY) /* WIP Bit of SPI SR */
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#define SPIFLASH_WE 1
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#define SPIFLASH_WE_BIT (1 << SPIFLASH_WE) /* WEL Bit of SPI SR */
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/* SPI Flash Commands */
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#define SPIFLASH_READ_ID 0x9F /* Read Flash Identification */
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#define SPIFLASH_READ_MID 0xAF /* Read Flash Identification, multi-io */
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#define SPIFLASH_READ_STATUS 0x05 /* Read Status Register */
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#define SPIFLASH_WRITE_ENABLE 0x06 /* Write Enable */
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#define SPIFLASH_PAGE_PROGRAM 0x02 /* Page Program */
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#define SPIFLASH_FAST_READ 0x0B /* Fast Read */
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#define SPIFLASH_READ 0x03 /* Normal Read */
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#define SPIFLASH_MASS_ERASE 0xC7 /* Mass Erase */
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#define SPIFLASH_READ_SFDP 0x5A /* Read Serial Flash Discoverable Parameters */
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#define SPIFLASH_DEF_PAGESIZE 256 /* default for non-page-oriented devices (FRAMs) */
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#endif /* OPENOCD_FLASH_NOR_SPI_H */
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