3799eded67
GDB can be built for multi-architecture through the command
./configure --enable-targets=all && make
Such multi-architecture GDB requires the target's architecture to
be selected either manually by the user through the GDB command
"set architecture" or automatically by the target description sent
by the remote target (i.e. OpenOCD).
Commit e65acd889c ("gdb_server: add
support for architecture element") already provides the required
infrastructure to support multi-architecture gdb.
aarch64-linux-gnu-gdb 8.2 uses "aarch64" as default architecture,
but also supports the value "aarch64:ilp32" and all the values
supported by arm-none-eabi-gdb.
These values can be displayed on arm gdb prompt by typing
"set architecture " followed by a TAB for autocompletion.
Set the gdb architecture value for aarch64 target to "aarch64".
Change-Id: I63e9769f47d8e73f048eb84fa73e082dd1c8e52c
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/4755
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
304 lines
8.2 KiB
C
304 lines
8.2 KiB
C
/*
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* Copyright (C) 2005 by Dominic Rath
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* Dominic.Rath@gmx.de
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*
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* Copyright (C) 2008 by Spencer Oliver
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* spen@spen-soft.co.uk
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*
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* Copyright (C) 2009 by Øyvind Harboe
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* oyvind.harboe@zylin.com
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*
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* Copyright (C) 2018 by Liviu Ionescu
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* <ilg@livius.net>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef OPENOCD_TARGET_ARM_H
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#define OPENOCD_TARGET_ARM_H
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#include <helper/command.h>
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#include "target.h"
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/**
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* @file
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* Holds the interface to ARM cores.
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*
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* At this writing, only "classic ARM" cores built on the ARMv4 register
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* and mode model are supported. The Thumb2-only microcontroller profile
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* support has not yet been integrated, affecting Cortex-M parts.
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*/
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/**
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* Represent state of an ARM core.
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*
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* Most numbers match the five low bits of the *PSR registers on
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* "classic ARM" processors, which build on the ARMv4 processor
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* modes and register set.
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*
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* ARM_MODE_ANY is a magic value, often used as a wildcard.
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*
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* Only the microcontroller cores (ARMv6-M, ARMv7-M) support ARM_MODE_THREAD,
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* ARM_MODE_USER_THREAD, and ARM_MODE_HANDLER. Those are the only modes
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* they support.
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*/
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enum arm_mode {
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ARM_MODE_USR = 16,
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ARM_MODE_FIQ = 17,
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ARM_MODE_IRQ = 18,
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ARM_MODE_SVC = 19,
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ARM_MODE_MON = 22,
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ARM_MODE_ABT = 23,
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ARM_MODE_UND = 27,
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ARM_MODE_1176_MON = 28,
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ARM_MODE_SYS = 31,
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ARM_MODE_THREAD = 0,
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ARM_MODE_USER_THREAD = 1,
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ARM_MODE_HANDLER = 2,
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ARMV8_64_EL0T = 0x0,
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ARMV8_64_EL1T = 0x4,
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ARMV8_64_EL1H = 0x5,
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ARMV8_64_EL2T = 0x8,
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ARMV8_64_EL2H = 0x9,
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ARMV8_64_EL3T = 0xC,
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ARMV8_64_EL3H = 0xD,
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ARM_MODE_ANY = -1
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};
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/* VFPv3 internal register numbers mapping to d0:31 */
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enum {
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ARM_VFP_V3_D0 = 51,
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ARM_VFP_V3_D1,
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ARM_VFP_V3_D2,
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ARM_VFP_V3_D3,
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ARM_VFP_V3_D4,
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ARM_VFP_V3_D5,
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ARM_VFP_V3_D6,
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ARM_VFP_V3_D7,
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ARM_VFP_V3_D8,
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ARM_VFP_V3_D9,
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ARM_VFP_V3_D10,
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ARM_VFP_V3_D11,
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ARM_VFP_V3_D12,
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ARM_VFP_V3_D13,
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ARM_VFP_V3_D14,
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ARM_VFP_V3_D15,
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ARM_VFP_V3_D16,
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ARM_VFP_V3_D17,
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ARM_VFP_V3_D18,
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ARM_VFP_V3_D19,
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ARM_VFP_V3_D20,
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ARM_VFP_V3_D21,
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ARM_VFP_V3_D22,
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ARM_VFP_V3_D23,
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ARM_VFP_V3_D24,
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ARM_VFP_V3_D25,
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ARM_VFP_V3_D26,
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ARM_VFP_V3_D27,
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ARM_VFP_V3_D28,
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ARM_VFP_V3_D29,
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ARM_VFP_V3_D30,
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ARM_VFP_V3_D31,
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ARM_VFP_V3_FPSCR,
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};
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const char *arm_mode_name(unsigned psr_mode);
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bool is_arm_mode(unsigned psr_mode);
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/** The PSR "T" and "J" bits define the mode of "classic ARM" cores. */
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enum arm_state {
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ARM_STATE_ARM,
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ARM_STATE_THUMB,
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ARM_STATE_JAZELLE,
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ARM_STATE_THUMB_EE,
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ARM_STATE_AARCH64,
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};
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/** ARM vector floating point enabled, if yes which version. */
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enum arm_vfp_version {
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ARM_VFP_DISABLED,
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ARM_VFP_V1,
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ARM_VFP_V2,
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ARM_VFP_V3,
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};
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#define ARM_COMMON_MAGIC 0x0A450A45
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/**
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* Represents a generic ARM core, with standard application registers.
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*
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* There are sixteen application registers (including PC, SP, LR) and a PSR.
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* Cortex-M series cores do not support as many core states or shadowed
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* registers as traditional ARM cores, and only support Thumb2 instructions.
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*/
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struct arm {
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int common_magic;
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struct reg_cache *core_cache;
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/** Handle to the PC; valid in all core modes. */
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struct reg *pc;
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/** Handle to the CPSR/xPSR; valid in all core modes. */
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struct reg *cpsr;
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/** Handle to the SPSR; valid only in core modes with an SPSR. */
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struct reg *spsr;
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/** Support for arm_reg_current() */
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const int *map;
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/**
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* Indicates what registers are in the ARM state core register set.
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* ARM_MODE_ANY indicates the standard set of 37 registers,
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* seen on for example ARM7TDMI cores. ARM_MODE_MON indicates three
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* more registers are shadowed, for "Secure Monitor" mode.
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* ARM_MODE_THREAD indicates a microcontroller profile core,
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* which only shadows SP.
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*/
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enum arm_mode core_type;
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/** Record the current core mode: SVC, USR, or some other mode. */
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enum arm_mode core_mode;
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/** Record the current core state: ARM, Thumb, or otherwise. */
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enum arm_state core_state;
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/** Flag reporting unavailability of the BKPT instruction. */
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bool is_armv4;
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/** Flag reporting armv6m based core. */
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bool is_armv6m;
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/** Floating point or VFP version, 0 if disabled. */
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int arm_vfp_version;
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int (*setup_semihosting)(struct target *target, int enable);
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/** Backpointer to the target. */
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struct target *target;
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/** Handle for the debug module, if one is present. */
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struct arm_dpm *dpm;
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/** Handle for the Embedded Trace Module, if one is present. */
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struct etm_context *etm;
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/* FIXME all these methods should take "struct arm *" not target */
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/** Retrieve all core registers, for display. */
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int (*full_context)(struct target *target);
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/** Retrieve a single core register. */
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int (*read_core_reg)(struct target *target, struct reg *reg,
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int num, enum arm_mode mode);
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int (*write_core_reg)(struct target *target, struct reg *reg,
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int num, enum arm_mode mode, uint8_t *value);
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/** Read coprocessor register. */
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int (*mrc)(struct target *target, int cpnum,
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uint32_t op1, uint32_t op2,
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uint32_t CRn, uint32_t CRm,
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uint32_t *value);
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/** Write coprocessor register. */
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int (*mcr)(struct target *target, int cpnum,
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uint32_t op1, uint32_t op2,
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uint32_t CRn, uint32_t CRm,
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uint32_t value);
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void *arch_info;
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/** For targets conforming to ARM Debug Interface v5,
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* this handle references the Debug Access Port (DAP)
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* used to make requests to the target.
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*/
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struct adiv5_dap *dap;
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};
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/** Convert target handle to generic ARM target state handle. */
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static inline struct arm *target_to_arm(struct target *target)
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{
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assert(target != NULL);
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return target->arch_info;
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}
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static inline bool is_arm(struct arm *arm)
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{
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assert(arm != NULL);
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return arm->common_magic == ARM_COMMON_MAGIC;
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}
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struct arm_algorithm {
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int common_magic;
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enum arm_mode core_mode;
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enum arm_state core_state;
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};
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struct arm_reg {
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int num;
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enum arm_mode mode;
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struct target *target;
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struct arm *arm;
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uint8_t value[16];
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};
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struct reg_cache *arm_build_reg_cache(struct target *target, struct arm *arm);
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struct reg_cache *armv8_build_reg_cache(struct target *target);
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extern const struct command_registration arm_command_handlers[];
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int arm_arch_state(struct target *target);
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const char *arm_get_gdb_arch(struct target *target);
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int arm_get_gdb_reg_list(struct target *target,
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struct reg **reg_list[], int *reg_list_size,
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enum target_register_class reg_class);
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const char *armv8_get_gdb_arch(struct target *target);
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int armv8_get_gdb_reg_list(struct target *target,
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struct reg **reg_list[], int *reg_list_size,
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enum target_register_class reg_class);
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int arm_init_arch_info(struct target *target, struct arm *arm);
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/* REVISIT rename this once it's usable by ARMv7-M */
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int armv4_5_run_algorithm(struct target *target,
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int num_mem_params, struct mem_param *mem_params,
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int num_reg_params, struct reg_param *reg_params,
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target_addr_t entry_point, target_addr_t exit_point,
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int timeout_ms, void *arch_info);
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int armv4_5_run_algorithm_inner(struct target *target,
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int num_mem_params, struct mem_param *mem_params,
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int num_reg_params, struct reg_param *reg_params,
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uint32_t entry_point, uint32_t exit_point,
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int timeout_ms, void *arch_info,
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int (*run_it)(struct target *target, uint32_t exit_point,
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int timeout_ms, void *arch_info));
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int arm_checksum_memory(struct target *target,
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target_addr_t address, uint32_t count, uint32_t *checksum);
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int arm_blank_check_memory(struct target *target,
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struct target_memory_check_block *blocks, int num_blocks, uint8_t erased_value);
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void arm_set_cpsr(struct arm *arm, uint32_t cpsr);
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struct reg *arm_reg_current(struct arm *arm, unsigned regnum);
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struct reg *armv8_reg_current(struct arm *arm, unsigned regnum);
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extern struct reg arm_gdb_dummy_fp_reg;
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extern struct reg arm_gdb_dummy_fps_reg;
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#endif /* OPENOCD_TARGET_ARM_H */
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