3acb107b9a
- added access to ARM920T vector catch register (via generic register mechanism) - don't disable linefills on ARM920T cores - this lead to lockups when accessing lines already contained in cache - read content of ARM920T cache and tlb into file (arm920t read_flash/read_mmu commands) - memory reading improved on ARM7/9, can be further accelerated with new "arm7_9 fast_memory_access enable" command (renamed from fast_writes) - made in_handler independent from in field (makes the handler more flexible) - added timeout to ft2232 when using D2XX library - fixed STR7x protection bit handling on second bank (thanks to Bernard) - added support for using the OpenOCD on AT91RM9200 systems (thanks to Anders Larsen) - fixed AT91SAM7 flash handling when not running from 32kHz clock (thanks to Anders Larsen) git-svn-id: svn://svn.berlios.de/openocd/trunk@90 b42882b7-edfa-0310-969c-e2dbd0fdcd60
58 lines
2.4 KiB
C
58 lines
2.4 KiB
C
/***************************************************************************
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* Copyright (C) 2005 by Dominic Rath *
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* Dominic.Rath@gmx.de *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, write to the *
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* Free Software Foundation, Inc., *
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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***************************************************************************/
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#ifndef ARMV4_5_CACHE_H
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#define ARMV4_5_CACHE_H
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#include "types.h"
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#include "command.h"
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typedef struct armv4_5_cachesize_s
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{
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int linelen;
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int associativity;
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int nsets;
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int cachesize;
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} armv4_5_cachesize_t;
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typedef struct armv4_5_cache_common_s
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{
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int ctype; /* specify supported cache operations */
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int separate; /* separate caches or unified cache */
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armv4_5_cachesize_t d_u_size; /* data cache */
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armv4_5_cachesize_t i_size; /* instruction cache */
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int i_cache_enabled;
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int d_u_cache_enabled;
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} armv4_5_cache_common_t;
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extern int armv4_5_identify_cache(u32 cache_type_reg, armv4_5_cache_common_t *cache);
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extern int armv4_5_cache_state(u32 cp15_control_reg, armv4_5_cache_common_t *cache);
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extern int armv4_5_handle_cache_info_command(struct command_context_s *cmd_ctx, armv4_5_cache_common_t *armv4_5_cache);
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enum
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{
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ARMV4_5_D_U_CACHE_ENABLED = 0x4,
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ARMV4_5_I_CACHE_ENABLED = 0x1000,
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ARMV4_5_WRITE_BUFFER_ENABLED = 0x8,
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ARMV4_5_CACHE_RR_BIT = 0x5000,
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};
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#endif /* ARMV4_5_CACHE_H */
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