Tim Newsome 3ba21e5f00 target/riscv: calloc() memory per register. ... This replaces a static array with 8 bytes per register. When there are vector registers larger than 8 bytes, they would end up clobbering each other's values. I can't believe I didn't catch this earlier. See https://github.com/riscv/riscv-openocd/pull/658 Change-Id: I9df4eaf05617a2c8df3140fff9fe53f61ab2b261 Signed-off-by: Tim Newsome <tim@sifive.com> Reviewed-on: https://review.openocd.org/c/openocd/+/6775 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>		2021-12-24 15:10:20 +00:00
..
asm.h	Upstream tons of RISC-V changes.	2020-10-14 05:43:05 +01:00
batch.c	Upstream a whole host of RISC-V changes.	2021-10-25 16:12:05 +00:00
batch.h	Upstream tons of RISC-V changes.	2020-10-14 05:43:05 +01:00
debug_defines.h	riscv: Regenerated debug_defines.h and encoding.h	2021-11-20 14:39:13 +00:00
encoding.h	riscv: Regenerated debug_defines.h and encoding.h	2021-11-20 14:39:13 +00:00
gdb_regs.h	Upstream tons of RISC-V changes.	2020-10-14 05:43:05 +01:00
Makefile.am	Add RISC-V support.	2018-07-24 13:07:26 +01:00
opcodes.h	Upstream a whole host of RISC-V changes.	2021-10-25 16:12:05 +00:00
program.c	Upstream tons of RISC-V changes.	2020-10-14 05:43:05 +01:00
program.h	Upstream a whole host of RISC-V changes.	2021-10-25 16:12:05 +00:00
riscv_semihosting.c	Upstream a whole host of RISC-V changes.	2021-10-25 16:12:05 +00:00
riscv-011.c	Upstream a whole host of RISC-V changes.	2021-10-25 16:12:05 +00:00
riscv-013.c	target,flash: allow target_free_working_area on NULL area pointer	2021-12-03 21:59:20 +00:00
riscv.c	target/riscv: calloc() memory per register.	2021-12-24 15:10:20 +00:00
riscv.h	target/riscv: calloc() memory per register.	2021-12-24 15:10:20 +00:00