8850eb8f2c
The transport SWD uses the JTAG queue to assert/deassert the system reset srst. This is the major inconsistency that has to be removed to properly split JTAG and SWD. Introduce a new driver API, reset(), to controls both the signals trst and srst in the driver, skipping the JTAG queue. Put the new API in struct jtag_interface, even if in this patch it's used for SWD only; the goal is to get it reused by the other transports. Add the implementation of the API in all the drivers that implement SWD. Such implementation is almost the same of the old code in JTAG queue. Create a wrapper adapter_system_reset() to use the new API and remove the SWD specific swd_add_reset(). In the wrapper replace jtag_add_sleep() with jtag_sleep(), because the former uses the JTAG queue too. Rename the old jtag_add_reset() as legacy_jtag_add_reset() with the target to remove it when all drivers would be ported to the new reset API. Create a new jtag_add_reset() that calls the legacy function for drivers still on the old reset API. Use the new API also on JTAG transport for the drivers that can support both SWD and JTAG. For the moment, do not modify the implementation of JTAG-only drivers, which will continue using the usual method. This should be cleaned-up in future commits. Change-Id: I32331c88313f6059b25e12c6bb0156aebc1c074f Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/4895 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
282 lines
9.9 KiB
C
282 lines
9.9 KiB
C
/***************************************************************************
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* Copyright (C) 2009-2010 by David Brownell *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program. If not, see <http://www.gnu.org/licenses/>. *
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***************************************************************************/
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#ifndef OPENOCD_JTAG_SWD_H
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#define OPENOCD_JTAG_SWD_H
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#include <target/arm_adi_v5.h>
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/* Bits in SWD command packets, written from host to target
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* first bit on the wire is START
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*/
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#define SWD_CMD_START (1 << 0) /* always set */
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#define SWD_CMD_APnDP (1 << 1) /* set only for AP access */
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#define SWD_CMD_RnW (1 << 2) /* set only for read access */
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#define SWD_CMD_A32 (3 << 3) /* bits A[3:2] of register addr */
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#define SWD_CMD_PARITY (1 << 5) /* parity of APnDP|RnW|A32 */
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#define SWD_CMD_STOP (0 << 6) /* always clear for synch SWD */
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#define SWD_CMD_PARK (1 << 7) /* driven high by host */
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/* followed by TRN, 3-bits of ACK, TRN */
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/**
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* Construct a "cmd" byte, in lSB bit order, which swd_driver.read_reg()
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* and swd_driver.write_reg() methods will use directly.
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*/
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static inline uint8_t swd_cmd(bool is_read, bool is_ap, uint8_t regnum)
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{
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uint8_t cmd = (is_ap ? SWD_CMD_APnDP : 0)
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| (is_read ? SWD_CMD_RnW : 0)
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| ((regnum & 0xc) << 1);
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/* 8 cmd bits 4:1 may be set */
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if (parity_u32(cmd))
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cmd |= SWD_CMD_PARITY;
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/* driver handles START, STOP, and TRN */
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return cmd;
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}
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/* SWD_ACK_* bits are defined in <target/arm_adi_v5.h> */
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/*
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* The following sequences are updated to
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* ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031E
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*/
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/**
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* SWD Line reset.
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*
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* SWD Line reset is at least 50 SWCLK cycles with SWDIO driven high,
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* followed by at least two idle (low) cycle.
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* Bits are stored (and transmitted) LSB-first.
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*/
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static const uint8_t swd_seq_line_reset[] = {
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/* At least 50 SWCLK cycles with SWDIO high */
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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/* At least 2 idle (low) cycles */
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0x00,
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};
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static const unsigned swd_seq_line_reset_len = 64;
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/**
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* JTAG-to-SWD sequence.
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*
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* The JTAG-to-SWD sequence is at least 50 TCK/SWCLK cycles with TMS/SWDIO
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* high, putting either interface logic into reset state, followed by a
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* specific 16-bit sequence and finally a line reset in case the SWJ-DP was
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* already in SWD mode.
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* Bits are stored (and transmitted) LSB-first.
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*/
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static const uint8_t swd_seq_jtag_to_swd[] = {
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/* At least 50 TCK/SWCLK cycles with TMS/SWDIO high */
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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/* Switching sequence from JTAG to SWD */
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0x9e, 0xe7,
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/* At least 50 TCK/SWCLK cycles with TMS/SWDIO high */
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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/* At least 2 idle (low) cycles */
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0x00,
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};
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static const unsigned swd_seq_jtag_to_swd_len = 136;
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/**
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* SWD-to-JTAG sequence.
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*
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* The SWD-to-JTAG sequence is at least 50 TCK/SWCLK cycles with TMS/SWDIO
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* high, putting either interface logic into reset state, followed by a
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* specific 16-bit sequence and finally at least 5 TCK/SWCLK cycles with
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* TMS/SWDIO high to put the JTAG TAP in Test-Logic-Reset state.
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* Bits are stored (and transmitted) LSB-first.
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*/
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static const uint8_t swd_seq_swd_to_jtag[] = {
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/* At least 50 TCK/SWCLK cycles with TMS/SWDIO high */
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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/* Switching sequence from SWD to JTAG */
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0x3c, 0xe7,
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/* At least 5 TCK/SWCLK cycles with TMS/SWDIO high */
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0xff,
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};
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static const unsigned swd_seq_swd_to_jtag_len = 80;
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/**
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* SWD-to-dormant sequence.
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*
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* This is at least 50 SWCLK cycles with SWDIO high to put the interface
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* in reset state, followed by a specific 16-bit sequence.
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* Bits are stored (and transmitted) LSB-first.
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*/
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static const uint8_t swd_seq_swd_to_dormant[] = {
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/* At least 50 SWCLK cycles with SWDIO high */
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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/* Switching sequence from SWD to dormant */
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0xbc, 0xe3,
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};
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static const unsigned swd_seq_swd_to_dormant_len = 72;
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/**
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* Dormant-to-SWD sequence.
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*
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* This is at least 8 TCK/SWCLK cycles with TMS/SWDIO high to abort any ongoing
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* selection alert sequence, followed by a specific 128-bit selection alert
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* sequence, followed by 4 TCK/SWCLK cycles with TMS/SWDIO low, followed by
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* a specific protocol-dependent activation code. For SWD the activation code
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* is an 8-bit sequence. The sequence ends with a line reset.
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* Bits are stored (and transmitted) LSB-first.
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*/
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static const uint8_t swd_seq_dormant_to_swd[] = {
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/* At least 8 SWCLK cycles with SWDIO high */
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0xff,
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/* Selection alert sequence */
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0x92, 0xf3, 0x09, 0x62, 0x95, 0x2d, 0x85, 0x86,
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0xe9, 0xaf, 0xdd, 0xe3, 0xa2, 0x0e, 0xbc, 0x19,
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/*
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* 4 SWCLK cycles with SWDIO low ...
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* + SWD activation code 0x1a ...
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* + at least 8 SWCLK cycles with SWDIO high
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*/
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0xa0, /* ((0x00) & GENMASK(3, 0)) | ((0x1a << 4) & GENMASK(7, 4)) */
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0xf1, /* ((0x1a >> 4) & GENMASK(3, 0)) | ((0xff << 4) & GENMASK(7, 4)) */
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0xff,
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/* At least 50 SWCLK cycles with SWDIO high */
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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/* At least 2 idle (low) cycles */
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0x00,
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};
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static const unsigned swd_seq_dormant_to_swd_len = 224;
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/**
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* JTAG-to-dormant sequence.
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*
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* This is at least 5 TCK cycles with TMS high to put the interface
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* in test-logic-reset state, followed by a specific 31-bit sequence.
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* Bits are stored (and transmitted) LSB-first.
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*/
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static const uint8_t swd_seq_jtag_to_dormant[] = {
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/* At least 5 TCK cycles with TMS high */
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0xff,
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/*
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* Still one TCK cycle with TMS high followed by 31 bits JTAG-to-DS
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* select sequence 0xba, 0xbb, 0xbb, 0x33,
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*/
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0x75, /* ((0xff >> 7) & GENMASK(0, 0)) | ((0xba << 1) & GENMASK(7, 1)) */
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0x77, /* ((0xba >> 7) & GENMASK(0, 0)) | ((0xbb << 1) & GENMASK(7, 1)) */
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0x77, /* ((0xbb >> 7) & GENMASK(0, 0)) | ((0xbb << 1) & GENMASK(7, 1)) */
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0x67, /* ((0xbb >> 7) & GENMASK(0, 0)) | ((0x33 << 1) & GENMASK(7, 1)) */
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};
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static const unsigned swd_seq_jtag_to_dormant_len = 40;
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/**
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* Dormant-to-JTAG sequence.
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*
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* This is at least 8 TCK/SWCLK cycles with TMS/SWDIO high to abort any ongoing
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* selection alert sequence, followed by a specific 128-bit selection alert
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* sequence, followed by 4 TCK/SWCLK cycles with TMS/SWDIO low, followed by
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* a specific protocol-dependent activation code. For JTAG there are two
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* possible activation codes:
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* - "JTAG-Serial": 12 bits 0x00, 0x00
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* - "Arm CoreSight JTAG-DP": 8 bits 0x0a
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* We use "JTAG-Serial" only, which seams more generic.
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* Since the target TAP can be either in Run/Test Idle or in Test-Logic-Reset
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* states, Arm recommends to put the TAP in Run/Test Idle using one TCK cycle
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* with TMS low. To keep the sequence length multiple of 8, 8 TCK cycle with
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* TMS low are sent (allowed by JTAG state machine).
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* Bits are stored (and transmitted) LSB-first.
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*/
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static const uint8_t swd_seq_dormant_to_jtag[] = {
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/* At least 8 TCK/SWCLK cycles with TMS/SWDIO high */
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0xff,
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/* Selection alert sequence */
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0x92, 0xf3, 0x09, 0x62, 0x95, 0x2d, 0x85, 0x86,
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0xe9, 0xaf, 0xdd, 0xe3, 0xa2, 0x0e, 0xbc, 0x19,
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/*
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* 4 TCK/SWCLK cycles with TMS/SWDIO low ...
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* + 12 bits JTAG-serial activation code 0x00, 0x00
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*/
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0x00, 0x00,
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/* put the TAP in Run/Test Idle */
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0x00,
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};
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static const unsigned swd_seq_dormant_to_jtag_len = 160;
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struct swd_driver {
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/**
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* Initialize the debug link so it can perform SWD operations.
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*
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* As an example, this would switch a dual-mode debug adapter
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* into SWD mode and out of JTAG mode.
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*
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* @return ERROR_OK on success, else a negative fault code.
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*/
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int (*init)(void);
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/**
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* Queue a special SWDIO sequence.
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*
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* @param seq The special sequence to generate.
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* @return ERROR_OK if the sequence was queued, negative error if the
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* sequence is unsupported.
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*/
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int (*switch_seq)(enum swd_special_seq seq);
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/**
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* Queued read of an AP or DP register.
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*
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* @param Command byte with APnDP/RnW/addr/parity bits
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* @param Where to store value to read from register
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* @param ap_delay_hint Number of idle cycles that may be
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* needed after an AP access to avoid WAITs
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*/
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void (*read_reg)(uint8_t cmd, uint32_t *value, uint32_t ap_delay_hint);
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/**
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* Queued write of an AP or DP register.
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*
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* @param Command byte with APnDP/RnW/addr/parity bits
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* @param Value to be written to the register
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* @param ap_delay_hint Number of idle cycles that may be
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* needed after an AP access to avoid WAITs
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*/
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void (*write_reg)(uint8_t cmd, uint32_t value, uint32_t ap_delay_hint);
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/**
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* Execute any queued transactions and collect the result.
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*
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* @return ERROR_OK on success, Ack response code on WAIT/FAULT
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* or negative error code on other kinds of failure.
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*/
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int (*run)(void);
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/**
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* Configures data collection from the Single-wire
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* trace (SWO) signal.
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* @param swo true if SWO data collection should be routed.
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*
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* For example, some debug adapters include a UART which
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* is normally connected to a microcontroller's UART TX,
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* but which may instead be connected to SWO for use in
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* collecting ITM (and possibly ETM) trace data.
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*
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* @return ERROR_OK on success, else a negative fault code.
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*/
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int *(*trace)(bool swo);
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};
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int swd_init_reset(struct command_context *cmd_ctx);
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#endif /* OPENOCD_JTAG_SWD_H */
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