3c2eabd20f
- Replace '\([^_]\)u32' with '\1uint32_t'. - Replace '^u32' with 'uint32_t'. git-svn-id: svn://svn.berlios.de/openocd/trunk@2279 b42882b7-edfa-0310-969c-e2dbd0fdcd60
100 lines
3.9 KiB
C
100 lines
3.9 KiB
C
/***************************************************************************
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* Copyright (C) 2005 by Dominic Rath *
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* Dominic.Rath@gmx.de *
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* *
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* Copyright (C) 2006 by Magnus Lundin *
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* lundin@mlu.mine.nu *
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* *
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* Copyright (C) 2008 by Spencer Oliver *
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* spen@spen-soft.co.uk *
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* *
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* Copyright (C) 2009 by Dirk Behme *
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* dirk.behme@gmail.com - copy from cortex_m3 *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, write to the *
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* Free Software Foundation, Inc., *
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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***************************************************************************/
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#ifndef CORTEX_A8_H
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#define CORTEX_A8_H
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#include "register.h"
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#include "target.h"
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#include "armv7m.h"
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extern char* cortex_a8_state_strings[];
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#define CORTEX_A8_COMMON_MAGIC 0x411fc082
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#define CPUID 0x54011D00
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/* Debug Control Block */
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#define DCB_DHCSR 0x54011DF0
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#define DCB_DCRSR 0x54011DF4
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#define DCB_DCRDR 0x54011DF8
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#define DCB_DEMCR 0x54011DFC
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typedef struct cortex_a8_fp_comparator_s
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{
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int used;
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int type;
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uint32_t fpcr_value;
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uint32_t fpcr_address;
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} cortex_a8_fp_comparator_t;
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typedef struct cortex_a8_dwt_comparator_s
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{
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int used;
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uint32_t comp;
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uint32_t mask;
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uint32_t function;
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uint32_t dwt_comparator_address;
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} cortex_a8_dwt_comparator_t;
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typedef struct cortex_a8_common_s
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{
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int common_magic;
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arm_jtag_t jtag_info;
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/* Context information */
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uint32_t dcb_dhcsr;
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uint32_t nvic_dfsr; /* Debug Fault Status Register - shows reason for debug halt */
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uint32_t nvic_icsr; /* Interrupt Control State Register - shows active and pending IRQ */
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/* Flash Patch and Breakpoint (FPB) */
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int fp_num_lit;
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int fp_num_code;
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int fp_code_available;
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int fpb_enabled;
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int auto_bp_type;
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cortex_a8_fp_comparator_t *fp_comparator_list;
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/* Data Watchpoint and Trace (DWT) */
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int dwt_num_comp;
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int dwt_comp_available;
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cortex_a8_dwt_comparator_t *dwt_comparator_list;
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/* Interrupts */
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int intlinesnum;
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uint32_t *intsetenable;
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armv7m_common_t armv7m;
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void *arch_info;
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} cortex_a8_common_t;
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extern int cortex_a8_init_arch_info(target_t *target, cortex_a8_common_t *cortex_a8, jtag_tap_t *tap);
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int cortex_a8_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
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int cortex_a8_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
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#endif /* CORTEX_A8_H */
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