3e6f9e8d1e
The semantics of "-work-area-virt 0" (or phys) changed with the patch to require specifying physical or virtrual work area addresses. Specifying zero was previously a NOP. Now it means that address zero is valid. This patch addresses three related issues: - MMU-less processors should never specify work-area-virt; remove those specifications. Such processors include ARM7TDMI, Cortex-M3, and ARM966. - MMU-equipped processors *can* specify work-area-virt... but zero won't be appropriate, except in mischievous contexts (which hide null pointer exceptions). Remove those specs from those processors too. If any of those mappings is valid, someone will need to submit a patch adding it ... along with a comment saying what OS provides the mapping, and in which context. Example, say "works with Linux 2.6.30+, in kernel mode". (Note that ARM Linux doesn't map kernel memory to zero ...) - Clarify docs on that "-virt" and other work area stuff. Seems to me work-area-virt is quite problematic; not every operating system provides such static mappings; if they do, they're not in every MMU context... Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
128 lines
3.7 KiB
INI
128 lines
3.7 KiB
INI
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jtag_khz 4
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######################################
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# Target: Atmel AT91SAM9260
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######################################
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME at91sam9260
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}
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if { [info exists ENDIAN] } {
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set _ENDIAN $ENDIAN
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} else {
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set _ENDIAN little
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}
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if { [info exists CPUTAPID ] } {
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set _CPUTAPID $CPUTAPID
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} else {
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# force an error till we get a good number
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set _CPUTAPID 0x0792603f
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}
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reset_config trst_and_srst
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jtag_nsrst_delay 200
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jtag_ntrst_delay 200
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jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
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######################
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# Target configuration
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######################
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm926ejs
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$_TARGETNAME invoke-event halted
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# Internal sram1 memory
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$_TARGETNAME configure -work-area-phys 0x00300000 -work-area-size 0x1000 -work-area-backup 1
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scan_chain
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$_TARGETNAME configure -event reset-deassert-post {at91sam_init}
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# Flash configuration
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#flash bank cfi <base> <size> <chip width> <bus width> <target#>
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flash bank cfi 0x10000000 0x01000000 2 2 $_TARGETNAME
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proc at91sam_init { } {
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# at reset chip runs at 32khz
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jtag_khz 8
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halt
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mww 0xfffffd08 0xa5000501 # RSTC_MR : enable user reset
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mww 0xfffffd44 0x00008000 # WDT_MR : disable watchdog
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mww 0xfffffc20 0x00004001 # CKGR_MOR : enable the main oscillator
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sleep 20 # wait 20 ms
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mww 0xfffffc30 0x00000001 # PMC_MCKR : switch to main oscillator
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sleep 10 # wait 10 ms
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mww 0xfffffc28 0x2060bf09 # CKGR_PLLAR: Set PLLA Register for 198,656MHz
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sleep 20 # wait 20 ms
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mww 0xfffffc30 0x00000101 # PMC_MCKR : Select prescaler
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sleep 10 # wait 10 ms
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mww 0xfffffc30 0x00000102 # PMC_MCKR : Clock from PLLA is selected
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sleep 10 # wait 10 ms
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# Now run at anything fast... ie: 10mhz!
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jtag_khz 10000 # Increase JTAG Speed to 6 MHz
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arm7_9 dcc_downloads enable # Enable faster DCC downloads
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mww 0xffffec00 0x0a0a0a0a # SMC_SETUP0 : Setup SMC for Intel NOR Flash JS28F128P30T85 128MBit
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mww 0xffffec04 0x0b0b0b0b # SMC_PULSE0
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mww 0xffffec08 0x00160016 # SMC_CYCLE0
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mww 0xffffec0c 0x00161003 # SMC_MODE0
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flash probe 0 # Identify flash bank 0
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mww 0xfffff870 0xffff0000 # PIO_ASR : Select peripheral function for D15..D31
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mww 0xfffff804 0xffff0000 # PIO_PDR : Disable PIO function for D15..D31
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mww 0xffffef1c 0x2 # EBI_CSA : Assign EBI Chip Select 1 to SDRAM
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mww 0xffffea08 0x85227259 # SDRAMC_CR : Configure SDRAM (2 x Samsung K4S561632H-UC75 : 4M x 16Bit x 4 Banks)
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#mww 0xffffea08 0x85227254 # SDRAMC_CR : Configure SDRAM (2 x Samsung K4S641632H-UC75 : 1M x 16Bit x 4 Banks)
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mww 0xffffea00 0x1 # SDRAMC_MR : issue a NOP command
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mww 0x20000000 0
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mww 0xffffea00 0x2 # SDRAMC_MR : issue an 'All Banks Precharge' command
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mww 0x20000000 0
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mww 0xffffea00 0x4 # SDRAMC_MR : issue 8 x 'Auto-Refresh' Command
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mww 0x20000000 0
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mww 0xffffea00 0x4
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mww 0x20000000 0
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mww 0xffffea00 0x4
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mww 0x20000000 0
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mww 0xffffea00 0x4
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mww 0x20000000 0
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mww 0xffffea00 0x4
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mww 0x20000000 0
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mww 0xffffea00 0x4
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mww 0x20000000 0
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mww 0xffffea00 0x4
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mww 0x20000000 0
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mww 0xffffea00 0x4
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mww 0x20000000 0
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mww 0xffffea00 0x3 # SDRAMC_MR : issue a 'Load Mode Register' command
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mww 0x20000000 0
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mww 0xffffea00 0x0 # SDRAMC_MR : normal mode
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mww 0x20000000 0
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mww 0xffffea04 0x5d2 # SDRAMC_TR : Set refresh timer count to 15us
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}
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